SpaceX

5 months ago

Principal DFT Engineer (Silicon Engineering)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 11 hours agoStatus: Live

Job Summary

Lead the design and optimization of DFT architectures for next-generation space-grade ASICs, including scan insertion, memory BIST, and ATPG tooling, while coordinating across cross-disciplinary teams to ensure RTL, physical design, and test readiness for SpaceX Starlink silicon deployments.

Location: Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Lead the implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
•Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
•Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
•Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
•Run and debug non-timing and SDF annotated gate level simulations

Pay and Benefits

Salary: USD 210,000 - 280,000 annually

Equity and Bonus:Equity

Perks:MedicalVisionDental401kEquityParental LeavePaid Leave

Key Requirements

•Bachelor's degree in electrical engineering, computer engineering or computer science.
•10+ years of experience working with ASICs.
•10+ years of experience in scan insertion and DFT setup, integration and validation.
•Leadership experience driving SOC DFT execution from concept through tapeout and product deployment.
•Strong implementation or integration of design blocks using Verilog/SystemVerilog.

Experience:10+ yearsSpaceAerospaceTelecommunications

Education:Bachelor's

Skills:PerlPythonTclCC++VerilogSystemVerilogDFTATPGUPFRTL

Languages:English

Tech Stack:VerilogSystemVerilogUPFATPGDFTRTLPerlPythonTclCC++

Eligibility

Nationality:US National

Company Brief

SpaceX

Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn

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SpaceX

5 months ago

Principal DFT Engineer (Silicon Engineering)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 11 hours agoStatus: Live

Job Summary

Location: Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Lead the implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
•Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
•Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
•Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
•Run and debug non-timing and SDF annotated gate level simulations

Pay and Benefits

Salary: USD 210,000 - 280,000 annually

Equity and Bonus:Equity

Perks:MedicalVisionDental401kEquityParental LeavePaid Leave

Key Requirements

•Bachelor's degree in electrical engineering, computer engineering or computer science.
•10+ years of experience working with ASICs.
•10+ years of experience in scan insertion and DFT setup, integration and validation.
•Leadership experience driving SOC DFT execution from concept through tapeout and product deployment.
•Strong implementation or integration of design blocks using Verilog/SystemVerilog.

Experience:10+ yearsSpaceAerospaceTelecommunications

Education:Bachelor's

Skills:PerlPythonTclCC++VerilogSystemVerilogDFTATPGUPFRTL

Languages:English

Tech Stack:VerilogSystemVerilogUPFATPGDFTRTLPerlPythonTclCC++

Eligibility

Nationality:US National

Company Brief

SpaceX

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn