RET Layout/Mask Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Architect and develop Resolution Enhancement Techniques (RET) layouts that enable production-ready 28nm process technologies. Create and modify lithography/etch wafer test layouts, support OPC development and monitoring (including reticle and scribe modules), and define reticle measurement/disposition specifications. Collaborate with fabrication process engineering, integration, PDK, and other RET engineers, and develop automation to produce layouts for monitoring and evaluation across required fabs and technologies.

Location: Dallas

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Create layouts for setup, evaluation, and monitoring of lithography/etch wafer processes.
•Work with fabrication process engineering and integration teams to determine specifications and create/modify test features using design rules or existing layouts.
•Create layouts for OPC development/monitor, collaborating with RET engineers on test reticle layout and scribe modules for model calibration and recipe development.
•Create layouts for reticle measurement and disposition, working with RET engineers and the PDK team to define specifications and placement rules.
•Develop and implement automation for producing layouts.

Key Requirements

•Master's Degree.
•5+ years of experience in Layout/Mask design.
•Proficiency with EDA layout tools (Cadence suite, Synopsys, etc.) and scripting (Python, SKILL, Perl).
•Proficiency working with design or PDK development in a semiconductor environment.
•Strong lithography knowledge and OPC experience.

Experience:5+ yearsSemiconductorsComputational lithographyLithography28nm process technologiesOPC

Education:Master's

Skills:Problem-solvingAnalyticalCommunication

Tech Stack:Cadence suiteSynopsysPythonSKILLPerlEDA layout toolsOPCPDK

Company Brief

Texas Instruments

Industry: Electronics Manufacturing

Website

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Texas Instruments

1 month ago

RET Layout/Mask Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Location: Dallas

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Create layouts for setup, evaluation, and monitoring of lithography/etch wafer processes.
•Work with fabrication process engineering and integration teams to determine specifications and create/modify test features using design rules or existing layouts.
•Create layouts for OPC development/monitor, collaborating with RET engineers on test reticle layout and scribe modules for model calibration and recipe development.
•Create layouts for reticle measurement and disposition, working with RET engineers and the PDK team to define specifications and placement rules.
•Develop and implement automation for producing layouts.

Key Requirements

•Master's Degree.
•5+ years of experience in Layout/Mask design.
•Proficiency with EDA layout tools (Cadence suite, Synopsys, etc.) and scripting (Python, SKILL, Perl).
•Proficiency working with design or PDK development in a semiconductor environment.
•Strong lithography knowledge and OPC experience.

Experience:5+ yearsSemiconductorsComputational lithographyLithography28nm process technologiesOPC

Education:Master's

Skills:Problem-solvingAnalyticalCommunication

Tech Stack:Cadence suiteSynopsysPythonSKILLPerlEDA layout toolsOPCPDK

Company Brief

Texas Instruments

Industry: Electronics Manufacturing

Website