Cisco

3 weeks ago

ASIC DFT Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 2 hours agoStatus: Live

Job Summary

Join the Silicon One development organization as an ASIC Engineer focused on Design-for-Test (DFT). You’ll partner with front-end RTL and backend physical design teams to define DFT requirements early, implement DFT features for ATE and in-system test, and drive testability through implementation and post-silicon validation. You’ll also develop innovative DFT IP and contribute to re-usable test and debug strategies for next-generation networking silicon.

Location: San Jose, Austin

Workplace: Hybrid

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Mid level

Key Responsibilities

•Implement Hardware DFT features that support ATE, in-system test, debug, and diagnostics for designs.
•Develop innovative DFT IP and coordinate full chip design integration of testability features with RTL.
•Enable integration and validation of test logic across implementation and post-silicon validation flows with design, verification, and PD teams.
•Create innovative hardware DFT and physical design aspects for new silicon device models, including bare die and stacked die, driving reusable test and debug strategies.
•Craft solutions and debug with minimal mentorship throughout implementation and validation phases.

Pay and Benefits

Salary: USD 152,500 - 219,200 annually

Perks:Health InsuranceDentalVision401kParental LeaveDisability CoverageLife InsuranceEquityPaid HolidaysPaid Leave

Key Requirements

•Bachelor’s or Master’s degree in Electrical or Computer Engineering with at least 5 years of experience.
•Experience in DFT, test, and silicon engineering, including designing testability for chip architectures.
•Experience with JTAG protocols and Scan and BIST architectures, including memory BIST and boundary scan.
•Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime.
•Experience with gate-level simulation and debugging using VCS and other simulators.

Experience:5+ yearsDFTSilicon engineeringTest engineeringASIC

Education:Bachelor's in Electrical or Computer Engineering

Skills:CollaborationDebuggingProblem-solving

Tech Stack:Design-for-Test (DFT)RTLATEJTAGScanBISTMemory BISTBoundary scanATPGTestMaxTetramaxTessentPrimeTimeVCSGate-level simulationVerilogSystemVerilogSystem Verilog Logic EquivalencyP1687

Company Brief

Cisco

Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor

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Cisco

3 weeks ago

ASIC DFT Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 2 hours agoStatus: Live

Job Summary

Location: San Jose, Austin

Workplace: Hybrid

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Mid level

Key Responsibilities

•Implement Hardware DFT features that support ATE, in-system test, debug, and diagnostics for designs.
•Develop innovative DFT IP and coordinate full chip design integration of testability features with RTL.
•Enable integration and validation of test logic across implementation and post-silicon validation flows with design, verification, and PD teams.
•Create innovative hardware DFT and physical design aspects for new silicon device models, including bare die and stacked die, driving reusable test and debug strategies.
•Craft solutions and debug with minimal mentorship throughout implementation and validation phases.

Pay and Benefits

Salary: USD 152,500 - 219,200 annually

Perks:Health InsuranceDentalVision401kParental LeaveDisability CoverageLife InsuranceEquityPaid HolidaysPaid Leave

Key Requirements

•Bachelor’s or Master’s degree in Electrical or Computer Engineering with at least 5 years of experience.
•Experience in DFT, test, and silicon engineering, including designing testability for chip architectures.
•Experience with JTAG protocols and Scan and BIST architectures, including memory BIST and boundary scan.
•Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime.
•Experience with gate-level simulation and debugging using VCS and other simulators.

Experience:5+ yearsDFTSilicon engineeringTest engineeringASIC

Education:Bachelor's in Electrical or Computer Engineering

Skills:CollaborationDebuggingProblem-solving

Tech Stack:Design-for-Test (DFT)RTLATEJTAGScanBISTMemory BISTBoundary scanATPGTestMaxTetramaxTessentPrimeTimeVCSGate-level simulationVerilogSystemVerilogSystem Verilog Logic EquivalencyP1687

Company Brief

Cisco

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor