Principal Product Engineer – High-Speed IP SerDes

Cadence Design Systems
Seoul
Workplace: OnsiteFull timeFunction: Solutions Engineering & Sales EngineeringSkills: ["Technical leadership","Communication","Cross-functional collaboration","Root cause problem-solving","Stakeholder management"]

Own SerDes product engineering for high-performance interface IP subsystems, supporting UCIe, PCIe, USB, DPHY, Ethernet, DDR/LPDDR/GDDR, and HBM PHYs. Lead customer-facing technical discussions from pre-sales through pre-silicon integration, post-silicon bring-up, and deployment. Drive resolution of complex integration issues, run SoC integration reviews, lead RTL and gate-level simulation/timing closure strategy, and improve integration methodologies while mentoring engineers.

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Cadence Design Systems
Cadence Design Systems
2 days ago

Principal Product Engineer – High-Speed IP SerDes

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Last checked: 2 hours agoStatus: Live

Job Summary

Own SerDes product engineering for high-performance interface IP subsystems, supporting UCIe, PCIe, USB, DPHY, Ethernet, DDR/LPDDR/GDDR, and HBM PHYs. Lead customer-facing technical discussions from pre-sales through pre-silicon integration, post-silicon bring-up, and deployment. Drive resolution of complex integration issues, run SoC integration reviews, lead RTL and gate-level simulation/timing closure strategy, and improve integration methodologies while mentoring engineers.
Location: Seoul
Workplace: Onsite
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Act as primary product engineering owner for SerDes subsystems (PCIe, USB, Ethernet, etc) at the customer level.
  • •Lead customer engagements, including technical discussions, design reviews, and deployment activities.
  • •Own and drive resolution of complex subsystem integration and implementation issues.
  • •Provide technical leadership for RTL, gate-level simulations, and timing closure strategy.
  • •Lead post-silicon bring-up and debug to ensure successful customer deployment; collaborate with R&D, validation, and applications teams.

Key Requirements

  • •Strong experience with high-speed interface IP.
  • •Deep understanding of RTL design, gate-level verification, and simulation methodologies.
  • •Experience with synthesis, STA, and timing closure; backend knowledge is a plus.
  • •Familiarity with DFT methodologies, test flows, and system validation approaches.
  • •Bachelor’s (7+ years) or Master’s (5+ years) or PhD in electrical/computer engineering or related field, with relevant experience.
Education:
Skills:Technical leadershipCommunicationCross-functional collaborationRoot cause problem-solvingStakeholder management
Tech Stack:High-speed interface IPSerDesUCIePCIeUSBDPHYEthernetDDRLPDDRGDDRHBM PHYsRTLGate-level simulationGate-level verificationSynthesisSTATiming closureDFTTest flowsSystem validation

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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