Senior / Principal Layout Engineer – Module Architecture (Pathfinding)

Micron Technology
San Jose
Workplace: OnsiteFull timeUSD 202,000 - 344,000 annuallyFunction: Architecture & Urban PlanningExperience: 8-15 yearsEducation: bachelorsSkills: ["Ownership","Collaboration","Design review","Risk assessment","Mentorship"]

Drive layout-driven architecture exploration for next-generation memory modules and interconnects. Evaluate form factors, routing topology, and pinout tradeoffs to meet future bandwidth and density goals, translating routing complexity, layer count, and via strategies into feasible design envelopes. Collaborate with SI/PI teams to co-optimize channel topology and mitigation strategies, define SI/PI budgets, influence JEDEC standards, and help develop next-gen layout methodologies while mentoring junior engineers.

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FursaFursa
Micron Technology
Micron Technology
1 week ago

Senior / Principal Layout Engineer – Module Architecture (Pathfinding)

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Last checked: 12 hours agoStatus: Live

Job Summary

Drive layout-driven architecture exploration for next-generation memory modules and interconnects. Evaluate form factors, routing topology, and pinout tradeoffs to meet future bandwidth and density goals, translating routing complexity, layer count, and via strategies into feasible design envelopes. Collaborate with SI/PI teams to co-optimize channel topology and mitigation strategies, define SI/PI budgets, influence JEDEC standards, and help develop next-gen layout methodologies while mentoring junior engineers.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Architecture & Urban Planning
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead layout-driven architecture exploration for next-generation memory modules and interconnects.
  • •Evaluate form factor, routing topology, and pinout tradeoffs to enable future bandwidth and density targets.
  • •Define feasible design envelopes (routing complexity, layer count, escape feasibility, via strategy) and routing rules for extreme-speed interfaces.
  • •Collaborate with SI/PI teams to co-optimize channel topology, and loss/reflection/crosstalk mitigation, including return path integrity and reference plane design.
  • •Drive adoption of next-generation PCB technologies, influence SI/PI budgets, and conduct design reviews and risk assessments while mentoring junior engineers.

Pay and Benefits

Salary: USD 202,000 - 344,000 annually
Perks:Health InsuranceDentalVisionPaid LeavePaid Holidays

Key Requirements

  • •Bachelor’s degree in Electrical Engineering or related field.
  • •8–15+ years of experience in high-speed PCB layout with strong ownership of complex designs.
  • •Deep expertise in DDR/LPDDR memory interfaces (or similar ultra-high-speed parallel interfaces) and SI/PI for transmission lines, channel loss, and PDN/target impedance.
  • •Advanced proficiency with Cadence Allegro / OrCAD (or equivalent high-end layout tools).
  • •Ability to influence architecture decisions using physical design constraints in cross-functional architecture/pathfinding environments.
Experience:8-15 yearsSemiconductorMemory and storageHigh-speed PCB layoutDDR/LPDDRSI/PI co-designAdvanced PCB technologies
Education:Bachelor's
Skills:OwnershipCollaborationDesign reviewRisk assessmentMentorship
Tech Stack:Cadence AllegroOrCADDDR6LPDDR6LPDDR7MRDIMM Gen3MRDIMM Gen4SOCAMM2JEDECAI toolsHigh-speed PCBSI/PI co-designTarget impedancePDN designMicroviasStacked viasVia-in-padUltra-low-loss materialsHybrid bonding

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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