Senior Hardware Engineer - SoC Electrical Failure Analysis (Hybrid)

Cisco
San Jose
Workplace: HybridFull timeUSD 165,000 - 241,400 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 6+ yearsSkills: ["Collaboration","Analytical thinking","Problem-solving"]

Design, develop, and test complex ASICs supporting pre-silicon validation through post-silicon bring-up and manufacturing support. Lead failure analysis and drive improvements in performance, yield, and reliability. Create post-silicon validation plans, capture and interpret device and signal integrity measurements (waveforms, eye diagrams, jitter/BER, PDN), and validate behavior under real networking workloads. Contribute to chip screening test and observability software using Python and C++.

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FursaFursa
Cisco
Cisco
1 month ago

Senior Hardware Engineer - SoC Electrical Failure Analysis (Hybrid)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Design, develop, and test complex ASICs supporting pre-silicon validation through post-silicon bring-up and manufacturing support. Lead failure analysis and drive improvements in performance, yield, and reliability. Create post-silicon validation plans, capture and interpret device and signal integrity measurements (waveforms, eye diagrams, jitter/BER, PDN), and validate behavior under real networking workloads. Contribute to chip screening test and observability software using Python and C++.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Lead and participate in SoC electrical failure analysis to determine contributing factors and corrective actions.
  • •Drive activities to improve product performance, yield, and reliability.
  • •Define and refine post-silicon validation plans for functionality, performance characterization, and reliability.
  • •Capture, analyze, and interpret device and signal measurements (waveforms, eye diagrams, jitter, BER, PDN, power stability and noise) and validate system-level behavior under real workloads.
  • •Contribute to chip screening tests and the observability software library.

Pay and Benefits

Salary: USD 165,000 - 241,400 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kPaid ParentalLong-term DisabilityLife InsurancePaid HolidaysPaid LeaveSick Time

Key Requirements

  • •Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 6+ years relevant experience, or a Master’s degree with 3+ years, or a PhD with 1+ years.
  • •Experience in electrical post-silicon validation (e.g., Vmin, leakage, PVT characterization).
  • •Experience in SoC failure analysis and power/signal integrity for high-speed mixed-signal designs.
  • •Experience with DFT and/or SRAM design and integration.
  • •Experience driving SoC failure analysis efforts.
Experience:6+ years
Skills:CollaborationAnalytical thinkingProblem-solving
Tech Stack:PythonC++ASICOscilloscopesVNABERTLogic analyzersDFTSRAMMBIST

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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