Lead Application Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 5+ yearsEducation: bachelorsSkills: ["Cadence Virtuoso","Layout automation","Physical verification","Extraction","EMIR analysis","AI/ML tools","Scripting"]

Lead Application Engineer role focusing on analog IC layout and back-end flow, requiring deep understanding of analog design fundamentals, advanced node Virtuoso constraints, and scripting for layout automation. The position involves full responsibility from floorplanning to complex block layouts, physical verification, extraction and EMIR analysis, with Cadence Virtuoso expertise and potential chip integration and signoff. AI/ML tool exposure is a plus and extensive experience (5-10 years) is expected.

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Cadence Design Systems
Cadence Design Systems
4 months ago

Lead Application Engineer

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Last checked: 8 hours agoStatus: Live

Job Summary

Lead Application Engineer role focusing on analog IC layout and back-end flow, requiring deep understanding of analog design fundamentals, advanced node Virtuoso constraints, and scripting for layout automation. The position involves full responsibility from floorplanning to complex block layouts, physical verification, extraction and EMIR analysis, with Cadence Virtuoso expertise and potential chip integration and signoff. AI/ML tool exposure is a plus and extensive experience (5-10 years) is expected.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Manager level

Key Responsibilities

  • •Contribute to analog IC layout design and back-end flows from floorplanning to block-level layouts, ensuring design rule compliance and quality.
  • •Perform physical verification, extraction and EMIR analysis using Cadence Virtuoso and related tools.
  • •Develop and maintain scripts to automate layout tasks and improve design productivity.
  • •Collaborate on chip integration and signoff processes, supporting overall reliability of the IC design flow.
  • •Explore and apply AI/ML assisted tools to enhance layout efficiency and workflow automation.

Key Requirements

  • •B.Tech. or equivalent with 5 to 10 years of relevant experience
  • •strong understanding of analog layout design fundamentals and advanced node Virtuoso techfile constraints
  • •hands-on experience writing scripts to perform layout automation tasks
  • •knowledge of complete analog back-end flow from top level floorplanning to complex block level layouts, physical verification, extraction, EMIR analysis
  • •prior design experience using Cadence Custom IC Physical Design tools (Virtuoso) and flows including chip integration and signoff
Experience:5+ yearsEDASemiconductorsIC design
Education:Bachelor's
Skills:Cadence VirtuosoLayout automationPhysical verificationExtractionEMIR analysisAI/ML toolsScripting
Languages:English
Tech Stack:Cadence VirtuosoPhysical DesignEDAAutomationAI/ML

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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