Sr. Principal Product Engineer

Cadence Design Systems
California
Workplace: OnsiteFull timeUSD 143,500 - 266,500 annuallyFunction: Communications, PR & CommunityExperience: 2+ yearsEducation: mastersSkills: ["Communication","Problem-solving","Analysis","Debugging","Collaboration"]

Serve as a Product Engineer in the Digital and Signoff (DSG) group, partnering with R&D and customer engagement teams to support advanced chip design software tools. Provide technical place-and-route expertise, track and debug customer issues, and coordinate with R&D and release to resolve problems. Run design benchmarks, develop flows and solutions, and apply deep ASIC RTL-to-GDSII knowledge across timing closure, PPA optimization, and silicon signoff at 16nm and below.

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Cadence Design Systems
Cadence Design Systems
1 day ago

Sr. Principal Product Engineer

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Job Summary

Serve as a Product Engineer in the Digital and Signoff (DSG) group, partnering with R&D and customer engagement teams to support advanced chip design software tools. Provide technical place-and-route expertise, track and debug customer issues, and coordinate with R&D and release to resolve problems. Run design benchmarks, develop flows and solutions, and apply deep ASIC RTL-to-GDSII knowledge across timing closure, PPA optimization, and silicon signoff at 16nm and below.
Location: California
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Mid level

Key Responsibilities

  • •Support Cadence products in the Digital and Signoff team for customers and R&D
  • •Track, debug, and resolve customer issues with R&D and the release team
  • •Run design benchmarks and develop flows and solutions
  • •Provide technical expertise across the RTL to GDSII flow, including timing closure and PPA optimization
  • •Collaborate as a technical point of contact, communicating clearly with internal and external stakeholders

Pay and Benefits

Salary: USD 143,500 - 266,500 annually
Perks:Paid LeavePaid Holidays401kHealth InsuranceDentalVision

Key Requirements

  • •MS in EE with 2+ years of experience in Digital Implementation as a design engineer or product engineer
  • •Strong understanding of VLSI physical design and timing analysis, including clock tree synthesis and routing optimization
  • •Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 16nm and below nodes
  • •Solid understanding of hierarchical design methodologies and low power design
  • •Automation skills using Perl, Tcl, and shell scripting, with strong communication and analysis skills
Experience:2+ years
Education:Master's
Skills:CommunicationProblem-solvingAnalysisDebuggingCollaboration
Tech Stack:PerlTclShell scriptingRTLGDSIIClock tree synthesisTiming analysisEDA toolsSynthesisPhysical designSignoff

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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