New College Grad - AI Infrastructure & HBM Architecture Engineer

Micron Technology
United States
Workplace: OnsiteFull timeFunction: Architecture & Urban PlanningEducation: mastersSkills: ["Technical communication","Research synthesis"]

Work with senior engineers to explore next-generation AI memory and system environments, analyzing emerging compute, networking, and storage infrastructure trends. Contribute to HBM architecture analysis by collecting and synthesizing data to inform bandwidth and latency requirements, help develop simulation frameworks for AI cluster performance, and build first-order performance models. Support trend dashboards using CSP benchmarks and industry datasets, collaborating with DTPCO mentors on architectural intercept opportunities.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Micron Technology
Micron Technology
4 days ago

New College Grad - AI Infrastructure & HBM Architecture Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Work with senior engineers to explore next-generation AI memory and system environments, analyzing emerging compute, networking, and storage infrastructure trends. Contribute to HBM architecture analysis by collecting and synthesizing data to inform bandwidth and latency requirements, help develop simulation frameworks for AI cluster performance, and build first-order performance models. Support trend dashboards using CSP benchmarks and industry datasets, collaborating with DTPCO mentors on architectural intercept opportunities.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Architecture & Urban Planning
Seniority: Entry level

Key Responsibilities

  • •Research emerging trends in compute, networking, and storage infrastructure to anticipate how future AI workloads will evolve.
  • •Support HBM architecture analysis by collecting and synthesizing data to inform bandwidth, latency, and system-level memory requirements.
  • •Develop or refine simulation frameworks to model AI cluster performance and memory subsystem behavior.
  • •Build first-order performance models for HBM bandwidth, latency, GPU/CPU interactions, and memory hierarchy trade-offs.
  • •Create trend dashboards using CSP benchmarks and industry datasets, and collaborate with DTPCO mentors on architectural intercept opportunities.

Pay and Benefits

Perks:Health InsuranceDentalVisionPaid LeavePaid Holidays

Key Requirements

  • •Currently pursuing a Master’s degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • •Strong foundation in computer architecture, digital systems, and hardware/software interaction.
  • •Interest in memory subsystem design (HBM, DDR, caches) and how it impacts AI/ML workloads.
  • •Deep understanding of the LLM pipeline and critical bottlenecks.
  • •Programming experience in Python, C/C++, or similar languages.
Education:Master's
Skills:Technical communicationResearch synthesis
Tech Stack:PythonC/C++LLMHBMDDRCachesGPU/CPUSimulation frameworksCSP benchmarks

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
Glassdoor
Glassdoor: 3.7
WebsiteLinkedIn