2 months ago

Senior Analog Layout Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Design and implement best-in-class high-speed analog layouts for Ciena’s optical fiber transmission solutions, including DAC/ADC and SERDES macros for 112G and 224G in deep-submicron CMOS/BiCMOS. You’ll perform layout feasibility studies, execute floorplanning/placement/routing, and run verification checks (DRC/ANT/LVS/PERC/EM/IR) to ensure top-quality results. You’ll also evaluate layout tool/process improvements and provide status updates with the team.

Location: Ottawa

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Mid level

Key Responsibilities

•Conduct layout feasibility studies with senior analog designers, evaluating trade-offs to identify best solutions.
•Create layouts for assigned analog blocks using floor planning, placement, and routing steps.
•Perform thorough verification checks (DRC, ANT, LVS, PERC, EM, IR) to ensure high layout quality.
•Investigate new features in layout tools and processes to improve productivity.
•Provide regular status updates, participate in team meetings, and share learnings with the group.

Pay and Benefits

Salary: CAD 114,000 - 182,000 annually

Equity and Bonus:Equity

Perks:Health InsuranceDentalVision401kEmployee AssistanceEquityPaid Leave

Key Requirements

•Bachelor's degree in Electrical Engineering (or related field) with 1-5 years of relevant industry experience.
•Experience in custom analog and mixed-signal layout design using deep sub-micron CMOS devices (e.g., Finfet transistors).
•Experience designing analog/mixed-signal blocks such as ADC, DAC, PLL, and SERDES.
•Proficiency using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem) and layout flows for advanced technology nodes.
•Strong understanding of layout techniques (floorplanning, device matching, minimizing parasitics, RF shielding, EM/IR/ESD, high-frequency routing) and verification results (DRC/PERC/ANT/ERC/LVS).

Experience:1-5 years

Education:Bachelor's in Electrical Engineering

Skills:TeamworkCommunicationInterpersonal skillsAnalytical thinkingAttention to detail

Tech Stack:CMOSBiCMOSFinfetSERDESDACADCPLLCadence VirtuosoSiemens CalibreAnsys TotemDRCANTLVSPERCEMIRPERLSKILLESDRC delay

Company Brief

Ciena

Provides networking systems, software, and services that enable service providers, cloud operators, and enterprises to deliver high-capacity connectivity and adaptive network solutions worldwide.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Hanover, United States

Founded: 1992

Glassdoor: 3.8

Website LinkedIn

Loading job details...

Preparing the role view and application actions.

Ciena

2 months ago

Senior Analog Layout Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Location: Ottawa

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Mid level

Key Responsibilities

•Conduct layout feasibility studies with senior analog designers, evaluating trade-offs to identify best solutions.
•Create layouts for assigned analog blocks using floor planning, placement, and routing steps.
•Perform thorough verification checks (DRC, ANT, LVS, PERC, EM, IR) to ensure high layout quality.
•Investigate new features in layout tools and processes to improve productivity.
•Provide regular status updates, participate in team meetings, and share learnings with the group.

Pay and Benefits

Salary: CAD 114,000 - 182,000 annually

Equity and Bonus:Equity

Perks:Health InsuranceDentalVision401kEmployee AssistanceEquityPaid Leave

Key Requirements

•Bachelor's degree in Electrical Engineering (or related field) with 1-5 years of relevant industry experience.
•Experience in custom analog and mixed-signal layout design using deep sub-micron CMOS devices (e.g., Finfet transistors).
•Experience designing analog/mixed-signal blocks such as ADC, DAC, PLL, and SERDES.
•Proficiency using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem) and layout flows for advanced technology nodes.
•Strong understanding of layout techniques (floorplanning, device matching, minimizing parasitics, RF shielding, EM/IR/ESD, high-frequency routing) and verification results (DRC/PERC/ANT/ERC/LVS).

Experience:1-5 years

Education:Bachelor's in Electrical Engineering

Skills:TeamworkCommunicationInterpersonal skillsAnalytical thinkingAttention to detail

Tech Stack:CMOSBiCMOSFinfetSERDESDACADCPLLCadence VirtuosoSiemens CalibreAnsys TotemDRCANTLVSPERCEMIRPERLSKILLESDRC delay

Company Brief

Ciena

Provides networking systems, software, and services that enable service providers, cloud operators, and enterprises to deliver high-capacity connectivity and adaptive network solutions worldwide.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Hanover, United States

Founded: 1992

Glassdoor: 3.8

Website LinkedIn