Staff Design Engineer

Work on multiple phases of SOC physical design, including floorplanning, partitioning, placement, clock tree synthesis, routing, and physical verification (LVS/DRC/ERC/Antenna). Own congestion, timing, and area closure by running equivalence checks, STA, crosstalk/noise analysis, and power optimization. Implement timing/functional ECOs, resolve congestion, and perform formal verification and timing analysis while collaborating with a global team using industry EDA tools.