RTL Design Engineer – FPGA High-Speed Connectivity IP

Join the FPGA Connectivity IP team to architect, design, develop, and validate high-performance RTL IP enabling next-generation FPGA connectivity. Work across the product development lifecycle from requirements and microarchitecture through RTL implementation, verification, and silicon enablement. Collaborate with architecture, verification, software, and system teams across geographies, performing timing analysis, formal checking, and debugging for advanced high-speed I/O subsystems.