Principal Design Engineer ( Layout Design )

Cadence Design Systems
Pune
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8-10 yearsEducation: bachelorsSkills: ["Communication","Teamwork","Analytical thinking","Problem-solving","Documentation"]

Own custom analog layout work for DDR IO development, partnering with the design team to deliver high-quality analog layouts. Perform physical verification (DRC/LVS/Reliability) and resolve violations. Lead custom layout efforts for DDR IO, including mentoring a small engineering team to achieve successful IP delivery. Apply strong understanding of layout effects on speed, capacitance, power, and area across latest nodes (28nm and below).

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Cadence Design Systems
Cadence Design Systems
3 days ago

Principal Design Engineer ( Layout Design )

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Own custom analog layout work for DDR IO development, partnering with the design team to deliver high-quality analog layouts. Perform physical verification (DRC/LVS/Reliability) and resolve violations. Lead custom layout efforts for DDR IO, including mentoring a small engineering team to achieve successful IP delivery. Apply strong understanding of layout effects on speed, capacitance, power, and area across latest nodes (28nm and below).
Location: Pune
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Custom layout design for DDR IO development, understanding design requirements and delivering analog layouts.
  • •Perform physical verifications (DRC/LVS/Reliability) and fix violations.
  • •Lead custom DDR IO layout efforts and coordinate with the design team to deliver analog layouts.
  • •Lead and mentor a small team of engineers to achieve successful IP delivery.
  • •Apply knowledge of analog layout effects and techniques to support chip-level IP integration.

Key Requirements

  • •Hands-on analog layout experience across IP such as opamps, bandgaps, data converters, LDO, and PLL.
  • •Understand how layout impacts circuit characteristics like speed, capacitance, power, and area.
  • •Knowledge of analog layout techniques (e.g., matching, shielding) and layout-related constraints and IP integration at chip level.
  • •Good understanding of DSM technology methodology and issues, with experience on latest technology nodes (28nm and below) desired.
  • •Strong communication skills, ability to work as a team player, and scripting/automation experience is a plus.
Experience:8-10 years
Education:Bachelor's in Electrical/Electronic
Skills:CommunicationTeamworkAnalytical thinkingProblem-solvingDocumentation
Tech Stack:DDR IOAnalog layoutsDRCLVSReliabilityDSM technologyOpampsBandgapsData convertersLDOPLLSerdesFloorplan constraintsIP integration

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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