Lead Product Engineer: SoC Verification

Cadence Design Systems
Belo Horizonte
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceEducation: bachelorsSkills: ["Deep technical problem solving","Debugging","Collaboration","Problem solving","Technical troubleshooting"]

Lead the deployment and evolution of Portable Stimulus methodologies for complex SoC verification programs. Work with semiconductor design and verification teams to debug generation/solver issues, analyze system-level modeling challenges, and collaborate with Cadence R&D to improve Perspec and PSS standards. Drive scalable system-level verification methodologies across simulation, emulation, virtual platforms, firmware-driven verification, and post-silicon reuse, including emerging AI-assisted verification workflows.

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Cadence Design Systems
Cadence Design Systems
1 month ago

Lead Product Engineer: SoC Verification

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Source: Company careers pageValidated by: Fursa AI
Last checked: 51 minutes agoStatus: Live

Job Summary

Lead the deployment and evolution of Portable Stimulus methodologies for complex SoC verification programs. Work with semiconductor design and verification teams to debug generation/solver issues, analyze system-level modeling challenges, and collaborate with Cadence R&D to improve Perspec and PSS standards. Drive scalable system-level verification methodologies across simulation, emulation, virtual platforms, firmware-driven verification, and post-silicon reuse, including emerging AI-assisted verification workflows.
Location: Belo Horizonte
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Work directly with semiconductor design and verification teams to deploy Portable Stimulus methodologies in complex SoC programs.
  • •Debug difficult generation and solver issues involving constraints, resources, execution ordering, and scenario realization.
  • •Investigate real-world modeling challenges in large system-level PSS environments.
  • •Collaborate with Cadence R&D to diagnose tool issues, influence new features, and improve PSS standards.
  • •Develop reference models, internal knowledge, and best practices and support advanced system-level verification use cases (software-driven, device programming, reuse across simulation/emulation/post-silicon, and integration with virtual platforms and firmware).

Key Requirements

  • •Complete a Bachelor’s degree in Computer Science or a related area.
  • •Experience in SoC verification, validation, or verification methodology.
  • •Hands-on experience with SystemVerilog and UVM or embedded/bare-metal environments.
  • •Solid understanding of constrained-random verification and system-level test generation.
  • •Experience debugging complex verification environments.
Experience:SemiconductorSoC verificationEDA
Education:Bachelor's in Computer Science
Skills:Deep technical problem solvingDebuggingCollaborationProblem solvingTechnical troubleshooting
Tech Stack:Portable Stimulus (PSS)PerspecSystemVerilogUVMCC++PythonConstraintsSimulationEmulationVirtual platformsFirmware-driven verificationPost-silicon reuseAI-assisted verificationPCIeDDRNetworkingARM

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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