Cadence Design Systems

1 month ago

Lead Application Engineer – Digital Verification

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Lead and support Cadence digital verification solutions for customer projects and pre-sales engagements; collaborate with sales to scope opportunities; plan and manage technical evaluations with customers and internal teams; deliver trainings, product demonstrations, and expert-level support to ensure successful adoption.

Location: Ho Chi Minh City

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Seniority: Manager level

Key Responsibilities

•Act as a tech consultant to lead and support Cadence digital verification solution for customer projects or pre-sales engagements.
•Work closely with the sales team to identify, qualify, and scope opportunities for Cadence’s digital functional logic verification solutions.
•Understand customer goals and objectives, and plan, execute, and manage key technical evaluations in close collaboration with customers and internal teams.
•Proactively engage with existing and prospective customers to ensure successful adoption and deployment of Cadence verification technologies.
•Summarize project activities, status, and outcomes, and report effectively to management while sharing knowledge and best practices within the team.

Key Requirements

•Bachelor’s degree or higher in Computer Science, Electrical Engineering, or related field, with 5–10 years of relevant industry experience.
•5–10 years of hands-on experience and strong expertise in hardware design and/or verification methodologies.
•Solid hands-on verification experience using UVM, SystemVerilog, Verilog, VHDL, SystemC, and SystemVerilog Assertions (SVA).
•Hands-on experience with Cadence Verification IP or Jasper is a strong plus.
•Good understanding of code coverage and functional coverage concepts, tools, and technologies.

Experience:5-10 yearsHardwareVerificationDigital verification

Education:Bachelor's

Skills:Communication

Languages:English

Tech Stack:UVMSystemVerilogVerilogVHDLSystemCSVACadence Verification IPJasper

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

1 month ago

Lead Application Engineer – Digital Verification

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Location: Ho Chi Minh City

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Seniority: Manager level

Key Responsibilities

•Act as a tech consultant to lead and support Cadence digital verification solution for customer projects or pre-sales engagements.
•Work closely with the sales team to identify, qualify, and scope opportunities for Cadence’s digital functional logic verification solutions.
•Understand customer goals and objectives, and plan, execute, and manage key technical evaluations in close collaboration with customers and internal teams.
•Proactively engage with existing and prospective customers to ensure successful adoption and deployment of Cadence verification technologies.
•Summarize project activities, status, and outcomes, and report effectively to management while sharing knowledge and best practices within the team.

Key Requirements

•Bachelor’s degree or higher in Computer Science, Electrical Engineering, or related field, with 5–10 years of relevant industry experience.
•5–10 years of hands-on experience and strong expertise in hardware design and/or verification methodologies.
•Solid hands-on verification experience using UVM, SystemVerilog, Verilog, VHDL, SystemC, and SystemVerilog Assertions (SVA).
•Hands-on experience with Cadence Verification IP or Jasper is a strong plus.
•Good understanding of code coverage and functional coverage concepts, tools, and technologies.

Experience:5-10 yearsHardwareVerificationDigital verification

Education:Bachelor's

Skills:Communication

Languages:English

Tech Stack:UVMSystemVerilogVerilogVHDLSystemCSVACadence Verification IPJasper

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor