Graduate Talent (Analog Layout Engineer)

Work as an entry-level individual contributor on analog and mixed-signal IP development, supporting custom layout implementation and physical verification for analog blocks used in SoC and IP designs. Execute layout design under supervision, implement using Virtuoso/Custom Compiler (or equivalent), run and debug verification checks such as DRC/LVS, reliability, EM/IR, ESD, and latch-up as applicable. Help drive layout iterations, ECOs, signoff closure, and document issues for senior review.