Design Verification Manager

Lead SoC design verification (DV) and AVnV activities across pre/post silicon, FPGA, and Palladium environments within the MCU organization. Drive power-aware verification, GLS and AMS flows, RTL/GLS regression, coverage tracking, and design review execution. Partner with cross-site Digital Design, software, analog, and Test/Silicon Validation/Application Engineering teams, mentor team members, and improve verification methodologies by working with the EDA team to upgrade tools and flows.