Principal Design Engineer

Cadence Design Systems
Ireland
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Problem-solving","Communication","Teamwork","Cooperation"]

Provide technical leadership on the PMA design team for SERDES product development in Cork. You will design high-speed SERDES analog/mixed-signal IC circuit blocks (up to and beyond 112 Gbps) from concept through verification, collaborating with physical design engineers and leading circuit design and SERDES architecture efforts. Work with global teams across time zones and apply deep expertise in jitter and signal equalization techniques.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
1 week ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Provide technical leadership on the PMA design team for SERDES product development in Cork. You will design high-speed SERDES analog/mixed-signal IC circuit blocks (up to and beyond 112 Gbps) from concept through verification, collaborating with physical design engineers and leading circuit design and SERDES architecture efforts. Work with global teams across time zones and apply deep expertise in jitter and signal equalization techniques.
Location: Ireland
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design high-speed SERDES products on leading edge technology nodes (e.g., 5nm FinFET CMOS) up to and exceeding 112 Gbps.
  • •Develop analog/mixed-signal IC circuit blocks from concept/specification through final verification against customer specifications.
  • •Collaborate with physical design engineers to design IC circuit blocks and PMA sections.
  • •Provide technical leadership across circuit design and SERDES architectures.
  • •Partner with global teams across different time zones.
Travel: Low travel

Key Requirements

  • •Minimum 7 years of experience in CMOS SERDES or high-speed I/O IC design and development.
  • •BEng, MEng or PhD qualified.
  • •Working knowledge of common SERDES standards and their electrical requirements.
  • •Thorough understanding of jitter and signal equalization techniques.
  • •Proficient design experience across SERDES circuit blocks such as Driver, Receiver, Serializer, Deserializer, PLL, and clock distribution.
Experience:CMOSSERDESHigh-speed I/O
Education:Bachelor's
Skills:Problem-solvingCommunicationTeamworkCooperation
Tech Stack:SERDESCMOS5nm FinFETAnalog/mixed-signalJitterSignal equalizationPLLHigh-speed clock distributionBias and bandgapVoltage regulators

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor