AI Silicon Physical Design Engineer

Cerebras
Sunnyvale
Workplace: OnsiteFull timeUSD 150,000 - 250,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: mastersSkills: ["Ownership","Deep dive","Collaboration"]

Join a close-knit physical design team to synthesize, place, and route high-speed chip designs. Own physical design and implementation across the full flow, collaborating with RTL to integrate blocks into the full-chip architecture. Drive timing closure using STA and constraint drafting, optimize power/performance and area, and resolve DRC/LVS and IR/EM issues using tools such as ICV or Calibre. Enhance flows with Tcl and Python.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cerebras
Cerebras
1 year ago

AI Silicon Physical Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live

Job Summary

Join a close-knit physical design team to synthesize, place, and route high-speed chip designs. Own physical design and implementation across the full flow, collaborating with RTL to integrate blocks into the full-chip architecture. Drive timing closure using STA and constraint drafting, optimize power/performance and area, and resolve DRC/LVS and IR/EM issues using tools such as ICV or Calibre. Enhance flows with Tcl and Python.
Location: Sunnyvale
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Synthesize, place, and route high-speed designs across the physical design and implementation flow.
  • •Collaborate closely with RTL teams to integrate physical design blocks into the full-chip architecture.
  • •Drive block and full-chip timing closure using STA, constraint drafting, and timing convergence methods.
  • •Optimize designs for power/performance and area through physical design iteration.
  • •Resolve DRC/LVS issues and address IR/EM analysis and resolution for blocks and the full chip.

Pay and Benefits

Salary: USD 150,000 - 250,000 annually

Key Requirements

  • •10+ years of physical design and physical verification experience.
  • •Strong block/subsystem timing closure skills using STA, constraint drafting, and timing convergence.
  • •Expertise with ICV or Calibre tools to resolve block and full-chip DRC and LVS issues.
  • •Expertise in IR/EM analysis and resolution, and optimizing for power/performance and area.
  • •Scripting skills in Tcl and Python; experience with Design Compiler, Fusion Compiler, ICC2 (or similar) and BS or MS in Electrical Engineering.
Experience:10+ yearsSemiconductorHardwareAI chipsAI infrastructure
Education:Master's in Electrical Engineering
Skills:OwnershipDeep diveCollaboration
Tech Stack:TclPythonICVCalibreDesign CompilerFusion CompilerICC2STADRCLVSIR/EM

Company Brief

Cerebras
Designs and builds wafer-scale AI accelerators and systems for large-scale deep learning workloads, delivering specialized hardware and software to accelerate model training and inference for enterprises and research institutions.
Industry: Hardware Devices
Company Size: Large (251 to 1,000 employees)
Growth: Scaleup
Headquarters: Sunnyvale, United States
Founded: 2016
WebsiteLinkedIn