IP Design Verification Engineer

Intel
Penang
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 6+ yearsEducation: bachelorsSkills: ["Problem-solving","Debugging","Communication","Cross-functional collaboration"]

Collaborate with architects, RTL developers, and physical design teams to validate complex architectural and microarchitectural features. Own RTL validation for functional/DFx, define verification strategies and test plans, and build BFMs to verify protocol compliance. Implement assertions and coverage in SystemVerilog, run gate-level simulations, debug failures, analyze coverage gaps, and automate pre-silicon validation using Tcl/Tk/Perl/Python. Drive smooth IP integration with system/SoC teams.

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FursaFursa
Intel
Intel
1 day ago

IP Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 3 months ago

Job Summary

Collaborate with architects, RTL developers, and physical design teams to validate complex architectural and microarchitectural features. Own RTL validation for functional/DFx, define verification strategies and test plans, and build BFMs to verify protocol compliance. Implement assertions and coverage in SystemVerilog, run gate-level simulations, debug failures, analyze coverage gaps, and automate pre-silicon validation using Tcl/Tk/Perl/Python. Drive smooth IP integration with system/SoC teams.
Location: Penang
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own RTL validation for functional and/or DFx and define verification strategies, methodologies, and detailed test plans.
  • •Create BFMs to interface with the IP, monitor transactions, and verify protocol compliance.
  • •Implement and execute test cases, assertions, and functional coverage in SystemVerilog aligned to the verification plan.
  • •Set up and perform gate-level simulations to verify asynchronous and multi-cycle paths, then debug failures in RTL and GLS environments.
  • •Analyze functional and code coverage metrics to identify gaps, automate pre-silicon validation flows, and collaborate on IP integration with system/SoC teams.

Key Requirements

  • •Bachelor's or advanced degree in Electrical Engineering, Computer Engineering, or a related discipline.
  • •6+ years of experience with a Bachelor's degree (4+ with a Master's, 2+ with a PhD).
  • •Strong proficiency in SystemVerilog and verification methodologies such as OVM and UVM.
  • •Expertise in DDR protocols, particularly LPDDR5 and DDR5, across validation stages from specifications to coverage.
  • •Experience with RTL validation, logic design, DFx concepts, and IP microarchitecture debug methodologies; familiarity with VCS/DVE/Verdi and UNIX/shell scripting.
Experience:6+ years
Education:Bachelor's
Skills:Problem-solvingDebuggingCommunicationCross-functional collaboration
Tech Stack:SystemVerilogOVMUVMDDRLPDDR5DDR5RTL validationDFxVCSDVEVerdiUNIXShell scriptingCTclTkPerlPythonBFMAssertions

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
Glassdoor
Glassdoor: 3.8
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