AMD

1 day ago

DFT DV Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 10 hours agoStatus: Live

Job Summary

Own DFX design and implement advanced DFT/DFX features such as SSN, EDT, and ATPG for complex SoCs. Partner with DFX architecture and design teams to align requirements, then develop and verify DFX features end to end. Build IJTAG/IEEE 1687 instrumentation using ICL/PDL, perform ICL extraction and PDL retargeting, and validate scan/SSN architectures with gate-level simulation. Create automated DFX flows and leverage EDA tools for debug and characterization.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Own the DFX design and develop DFX features including SSN, EDT, and ATPG for tile and SoC (die/package) level implementation.
•Collaborate with DFX architecture/design teams and SoC teams to align DFX requirements, implement, and verify DFX features while accelerating existing processes.
•Develop and implement IJTAG/IEEE 1687-based instrumentation using ICL and PDL, including managing test instruments and creating connectivity models.
•Perform DFX/DV verification by verifying SSN and scan architectures with gate-level simulations, validating scan patterns, and integrating test bench work with SV-based test benches.
•Implement and deploy automated design flows for end-to-end DFX development using scripting tools (Perl, Python, or TCL) and strong EDA/debug skills.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

•Own DFX design work, including ASIC DFX concepts and SSN, EDT, and ATPG experience at tile and SoC (die/package) level.
•Expertise writing custom ICL and PDL, including IJTAG/IEEE 1687 instrumentation to configure SSN and manage test instruments.
•Experience with ICL extraction and PDL retargeting from RTL/gate netlist through IP level to top level, with EDT/SSN/SSH architecture understanding.
•Strong DFX/DV verification experience validating scan/SSN architectures using gate-level simulations and TAP/JTAG-related DV features.
•Hands-on EDA and flow experience with Tessent tools (Testkompress, SSN, IJTAG, EDT) plus RTL quality checks such as Spyglass and Lint.

Experience:ASIC DFXSoCDFX/DVScan/ATPG

Education:Master's in Electrical/Electronics Engineering, Computer Engineering

Skills:CommunicationCollaborationProblem-solvingDebugging

Languages:English

Tech Stack:DFXDFTSSNEDTATPGTAP/JTAGIJTAGIEEE 1687ICLPDLTestKompressTessentSpyglassLintRTLGate netlistSystemVerilogUVMPerlPython

Company Brief

AMD

Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1969

Glassdoor: 3.9

Website LinkedIn

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AMD