Cisco

1 month ago

ASIC Physical Design Technical Lead

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Lead and optimize fullchip physical design flows for ASICs in Cisco CHG, driving floorplanning, clocking, and power integrity across 7nm/5nm/3nm processes. Collaborate with RTL, DFT, and EDA vendors to deliver high-performance, low-power silicon with efficient tool flows, and leverage AI/prompts to boost productivity.

Location: San Jose, Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Manager level

Key Responsibilities

•Fullchip floorplan by understanding architecture, foundry guidelines, and IP placement constraints and integrating into the fullchip floorplan
•Collaborate with system and package design teams to understand requirements and incorporate into floorplan
•Perform hierarchical implementation flow including partition, pin assignment, clock plan and bump planning; hands-on with fullchip clock mesh and Flex-HTree methods
•RTL-to-GDSII implementation: Floorplan, Power Grid planning, place and route, static timing analysis, power integrity, physical verification and equivalence checks focusing on performance, power, and die size
•Analyze tool flows and methodologies to identify efficiency gaps and implement improvements

Key Requirements

•Bachelor’s Degree in Electrical Engineering with 8+ years of Physical Design experience, or Master’s Degree with 6+ years, or PhD with 3+ years of Physical Design experience
•Experience working on Fullchip activities
•Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies
•Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus
•Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis

Experience:SemiconductorsHardwareSiliconChip design

Education:High School

Skills:InnovusTempusPrimetimeCalibrePegasusUPFPython

Tech Stack:InnovusTempusPrimetimeCalibrePegasusUPFPython

Company Brief

Cisco

Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor

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Cisco

1 month ago

ASIC Physical Design Technical Lead

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: San Jose, Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Manager level

Key Responsibilities

•Fullchip floorplan by understanding architecture, foundry guidelines, and IP placement constraints and integrating into the fullchip floorplan
•Collaborate with system and package design teams to understand requirements and incorporate into floorplan
•Perform hierarchical implementation flow including partition, pin assignment, clock plan and bump planning; hands-on with fullchip clock mesh and Flex-HTree methods
•RTL-to-GDSII implementation: Floorplan, Power Grid planning, place and route, static timing analysis, power integrity, physical verification and equivalence checks focusing on performance, power, and die size
•Analyze tool flows and methodologies to identify efficiency gaps and implement improvements

Key Requirements

•Bachelor’s Degree in Electrical Engineering with 8+ years of Physical Design experience, or Master’s Degree with 6+ years, or PhD with 3+ years of Physical Design experience
•Experience working on Fullchip activities
•Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies
•Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus
•Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis

Experience:SemiconductorsHardwareSiliconChip design

Education:High School

Skills:InnovusTempusPrimetimeCalibrePegasusUPFPython

Tech Stack:InnovusTempusPrimetimeCalibrePegasusUPFPython

Company Brief

Cisco

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor