Principal Product Engineer

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 140,000 - 260,000 annuallyFunction: Communications, PR & CommunityExperience: 5+ yearsEducation: mastersSkills: ["Communication","Analysis","Problem-solving","Teamwork"]

Serve as a Product Engineer for the Digital and Signoff Group (DSG), combining deep ASIC/physical design expertise with hands-on customer support. Support Cadence digital and signoff products by tracking and debugging customer issues with R&D and release teams, running design benchmarks, and building/optimizing flows and solutions across the RTL-to-GDSII flow. Bring strong timing-closure and PPA optimization experience for 16nm and below nodes.

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Cadence Design Systems
Cadence Design Systems
18 hours ago

Principal Product Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live
Reposted: similar role first listed 9 months ago

Job Summary

Serve as a Product Engineer for the Digital and Signoff Group (DSG), combining deep ASIC/physical design expertise with hands-on customer support. Support Cadence digital and signoff products by tracking and debugging customer issues with R&D and release teams, running design benchmarks, and building/optimizing flows and solutions across the RTL-to-GDSII flow. Bring strong timing-closure and PPA optimization experience for 16nm and below nodes.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Mid level

Key Responsibilities

  • •Support Cadence products in the Digital and Signoff team
  • •Track and debug customer issues and coordinate with R&D and release teams to resolve them
  • •Run design benchmarks and develop flows and solutions
  • •Provide technical place-and-route expertise to customers and R&D
  • •Develop and optimize solutions for advanced chip design platforms

Pay and Benefits

Salary: USD 140,000 - 260,000 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid Holidays401kMedicalDentalVisionEquity

Key Requirements

  • •MS in EE with 5+ years of experience in Digital Implementation as a design engineer or product engineer
  • •Strong understanding of VLSI physical design and timing analysis, including clock tree synthesis and routing optimization
  • •Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 16nm and below nodes
  • •Exposure to hierarchical design methodologies and solid understanding of low power design
  • •Strong communication, analysis, and problem-solving skills
Experience:5+ yearsASIC designVLSI physical designEDA tools
Education:Master's in EE
Skills:CommunicationAnalysisProblem-solvingTeamwork
Tech Stack:ASIC design methodologiesRTL to GDSIITiming closurePPA optimization16nmVLSI physical designTiming analysisClock tree synthesisRouting optimizationSilicon signoffHierarchical designLow power designSynthesisPhysical designSignoffPerlTclShell scriptingDesign benchmarksFlows

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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