Sr . STA / Timing constraints Engineer

AMD
Bengaluru
Workplace: OnsiteFull timeINR 2,186,520 - 3,123,600 annuallyFunction: Data Science & Machine LearningExperience: 5+ yearsEducation: bachelorsSkills: []

Develop and maintain complex multi-mode, multi-corner timing constraints compatible with RTL and signoff. Ensure SDC constraint quality using tools like Fishtail and GCA, run pre-route timing checks, and drive QoR cleanups to eliminate SDC issues. Own timing closure for one or more sub-chips/subsystems or full chips, including interface timing and DRV closure. Generate timing ECOs using DMSA/Tweaker and lead subsystem/full-chip timing closure.

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FursaFursa
AMD
AMD
6 days ago

Sr . STA / Timing constraints Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 52 minutes agoStatus: Live

Job Summary

Develop and maintain complex multi-mode, multi-corner timing constraints compatible with RTL and signoff. Ensure SDC constraint quality using tools like Fishtail and GCA, run pre-route timing checks, and drive QoR cleanups to eliminate SDC issues. Own timing closure for one or more sub-chips/subsystems or full chips, including interface timing and DRV closure. Generate timing ECOs using DMSA/Tweaker and lead subsystem/full-chip timing closure.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Data Science & Machine Learning
Seniority: Mid level

Key Responsibilities

  • •Develop multi-mode/multi-corner timing constraints compatible for RTL and signoff.
  • •Ensure SDC constraint quality using industry tools (e.g., Fishtail, GCA).
  • •Perform pre-route timing checks and QoR cleanup to remove SDC issues for STA handoff.
  • •Drive timing closure for one or more sub-chip/subsystem or full chip, including interface timing closure and DRV closure.
  • •Generate timing ECOs using tools like DMSA/Tweaker and lead subsystem/subchip/full-chip timing closure.

Pay and Benefits

Salary: INR 2,186,520 - 3,123,600 annually

Key Requirements

  • •5+ years building timing constraints for IPs, blocks, and full-chip implementation in flat/hierarchical flows.
  • •Experience analyzing timing reports to identify design and constraints-related issues.
  • •Preferred experience with Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker (or similar EDA tools).
  • •Strong understanding of SDC constraints and analysis methods such as OCV/AOCV/POCV, plus timing signoff methodologies and corner definitions.
  • •Strong TCL/scripting capability (EDA environment and standalone Linux Tcl shell scripts).
Experience:5+ years
Education:Bachelor's in Computer Engineering / Electrical Engineering
Tech Stack:SDCFishtailGCATclLinux TclSynopsys Design CompilerPrimetimeSpyglassDMSATweakerRTLSTASDC signoffOCVAOCVPOCV

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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