Cadence Design Systems

1 month ago

Lead Product Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 14 hours agoStatus: Live

Job Summary

Drive development of VIP products and verification IP across PCIe, UCIe, UALink and MIPI, supporting pre-sales activities for top-tier customers. Lead cross-functional programs, transfer product knowledge, translate customer requirements into specs, and collaborate with R&D/Marketing/support. Travel ~20% to engage with customers and events, shaping product direction and interoperability across complex systems.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Seniority: Manager level

Key Responsibilities

•Leads projects with high resource, risk and/or complexity
•Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results
•Stepping up on behalf of PE team during critical times and mitigating the risk
•Represent the PE team at different industry events and build the brand
•Develops and lead large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity
•Continually evaluates technology effectiveness/data interoperability of complex systems
•Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products
•Communicates highly complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view

Travel: Low travel

Pay and Benefits

Salary: USD 114,800 - 213,200 annually

Perks:Health InsuranceDentalVision401kPaid LeavePaid HolidaysEquity

Key Requirements

•BSc/BTech in Electrical, Electronics & Comm or Computer Science Engineering
•5 to 8 years of experience with Verification and Design
•Working knowledge of PCIe, UCIe, UALink, and MIPI protocols
•Experience with Developing Verification environments using SystemVerilog
•Working knowledge of the UVM methodology

Experience:5-8 yearsSemiconductorElectronic designIPVerification

Education:Bachelor's

Skills:SystemVerilogUVMVerificationDebuggingProblem-solvingCommunication

Tech Stack:PCIeUCIeUALinkMIPISystemVerilogUVM

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

1 month ago

Lead Product Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 14 hours agoStatus: Live

Job Summary

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Seniority: Manager level

Key Responsibilities

•Leads projects with high resource, risk and/or complexity
•Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results
•Stepping up on behalf of PE team during critical times and mitigating the risk
•Represent the PE team at different industry events and build the brand
•Develops and lead large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity
•Continually evaluates technology effectiveness/data interoperability of complex systems
•Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products
•Communicates highly complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view

Travel: Low travel

Pay and Benefits

Salary: USD 114,800 - 213,200 annually

Perks:Health InsuranceDentalVision401kPaid LeavePaid HolidaysEquity

Key Requirements

•BSc/BTech in Electrical, Electronics & Comm or Computer Science Engineering
•5 to 8 years of experience with Verification and Design
•Working knowledge of PCIe, UCIe, UALink, and MIPI protocols
•Experience with Developing Verification environments using SystemVerilog
•Working knowledge of the UVM methodology

Experience:5-8 yearsSemiconductorElectronic designIPVerification

Education:Bachelor's

Skills:SystemVerilogUVMVerificationDebuggingProblem-solvingCommunication

Tech Stack:PCIeUCIeUALinkMIPISystemVerilogUVM

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor