1 day ago

Lead Embedded CPU PPA Architect

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Last checked: 7 hours agoStatus: Live

Job Summary

Lead embedded CPU PPA (performance, power, and architecture) alignment for embedded products by translating product usage, workload, and reliability needs into CPU core/cache constraints. Drive cross-functional technical execution across CPU IP definition, embedded BU usage models, physical design implementation, FW/BIOS, SIPI, and platform teams. Own program-readiness inputs (power targets/BBox), close open performance/power items, and partner with power & performance modeling and reliability/thermal leads to meet aggressive targets.

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Mid level

Key Responsibilities

•Ensure CPU core/cache complexes for embedded products meet performance requirements within reliability and system platform constraints.
•Drive alignment across usage models and operating condition constraints to translate product needs into CPU IP performance, power, and thermal constraints.
•Lead alignment and technical reviews across the product definition stack (SoC architecture, physical design implementation, package design, and platform definition).
•Own program-readiness inputs and a structured open-items closure mechanism for performance and power topics, representing the workstream in program forums.
•Partner with power & performance modeling, power delivery, thermals, and reliability leads to align assumptions/targets and deliver decisions that meet aggressive operating objectives.

Pay and Benefits

Salary: USD 175,000 - 300,000 annually

Key Requirements

•BS/MS in EE/CE (or equivalent) with 7-10 years of relevant experience.
•Strong understanding of SoC architecture and design fundamentals, including rails, low power modes, and performance states.
•Working knowledge of PDN and PI principles (IR drop, droop, impedance, decaps, noise budgeting) and ability to drive closure with SIPI/packaging/platform partners.
•Working knowledge of device and system reliability requirements and thermal management algorithms.
•Demonstrated ability to lead complex cross-functional execution across architecture, FW/BIOS, validation, and package/platform.
•Familiarity collaborating with pre-silicon power & performance modeling teams and aligning assumptions/targets with projections.
•Experience with program milestone readiness and bringing a technical workstream to a review-ready state.

Experience:7-10 yearsEmbedded systemsSemiconductorsHigh-performance computing

Education:Master's in EE/CE

Skills:Technical leadershipCross-functional alignmentExecution-driven ownershipRisk managementProgram milestone readiness

Languages:English

Tech Stack:SoC architectureCPU IPCPU Core & CachePPAPower delivery network (PDN)PIIR dropDroopImpedanceDecapsNoise budgetingSIPIFW/BIOSPackagingPlatform definitionThermal modelingThermal management algorithmsReliability requirementsPower & performance modelingBBox (bounding box)

Company Brief

AMD

Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1969

Glassdoor: 3.9

Website LinkedIn

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AMD