Senior FPGA Verification Engineer

Anduril
United States
Workplace: OnsiteFull timeUSD 191,000 - 253,000 annuallyFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Technical leadership","Planning","Status reporting","Collaboration"]

Develop and mature FPGA verification for Imaging programs, including verification environment architecture, testbench development, and coverage-driven validation. Create test plans and test cases, track code and functional coverage, and apply assertion-based, constrained-random verification methodologies. Partner with an interdisciplinary team to define and execute verification activities, provide technical leadership, and contribute to program estimates—using SystemVerilog/VHDL and industry-standard simulation tools.

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Anduril
Anduril
7 hours ago

Senior FPGA Verification Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live
Reposted: similar role first listed 3 months ago

Job Summary

Develop and mature FPGA verification for Imaging programs, including verification environment architecture, testbench development, and coverage-driven validation. Create test plans and test cases, track code and functional coverage, and apply assertion-based, constrained-random verification methodologies. Partner with an interdisciplinary team to define and execute verification activities, provide technical leadership, and contribute to program estimates—using SystemVerilog/VHDL and industry-standard simulation tools.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Design and build FPGA verification environment architecture using SystemVerilog or OVM/UVM.
  • •Create written test plans and test cases, and track code coverage and functional coverage.
  • •Develop testbenches for verification of RTL blocks using VHDL or SystemVerilog.
  • •Recommend new tools and practices to continuously improve the ASIC/FPGA verification flow.
  • •Provide technical leadership to verification project teams by breaking down work, planning activities, and reporting status.

Pay and Benefits

Salary: USD 191,000 - 253,000 annually
Equity and Bonus:Equity

Key Requirements

  • •Typically requires a Bachelor’s in Electrical Engineering, Computer Engineering, or a related technical field.
  • •8+ years of experience developing HDL firmware for FPGA devices.
  • •Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
  • •Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
  • •Ability to apply chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog).
Experience:FPGAASICChip-level verificationDefense technologyImagingComputer vision
Education:Bachelor's
Skills:Technical leadershipPlanningStatus reportingCollaboration
Languages:English
Tech Stack:SystemVerilogOVM/UVMVHDLRTLFPGAASICVerilogAssertion-based verificationConstrained-random testingFunctional coverage analysisCode coverageGitSubversionUnix/LinuxScriptingCC++PythonPerlShell

Eligibility

Security Clearance:Secret

Company Brief

Anduril
Designs and builds advanced defense systems combining autonomous aircraft, sensors, and AI-driven software for military and national security applications, focused on modernizing battlefield capabilities and distributed sensing.
Industry: Defense Technology
Company Size: Enterprise (1,001+ employees)
Growth: Scaleup
Valuation: Unicorn (USD 1B+)
Funding: Series E+
Headquarters: Costa Mesa, United States
Founded: 2017
WebsiteLinkedIn