Product Development/DFX Lead - Neuromorphic Computing

Intel
Phoenix, Santa Clara, Austin
Workplace: HybridFull timeUSD 141,910 - 269,100 annuallyFunction: Administration & Executive AssistanceEducation: bachelorsSkills: []

Lead DFT/DFX strategy for Intel’s neuromorphic silicon program, architecting end-to-end manufacturing and test methodologies for Loihi’s asynchronous neuro-inspired designs. Drive scan-insertion and compression flows across partition and SoC levels, build scalable EDA/RTL/emulation-based test-vector frameworks pre-silicon, and collaborate with designers to deliver DFT features for HVM. Own power-on test enablement, debugging, and tool/flow reliability throughout the product lifecycle.

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Intel
Intel
4 days ago

Product Development/DFX Lead - Neuromorphic Computing

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Last checked: 53 minutes agoStatus: Live

Job Summary

Lead DFT/DFX strategy for Intel’s neuromorphic silicon program, architecting end-to-end manufacturing and test methodologies for Loihi’s asynchronous neuro-inspired designs. Drive scan-insertion and compression flows across partition and SoC levels, build scalable EDA/RTL/emulation-based test-vector frameworks pre-silicon, and collaborate with designers to deliver DFT features for HVM. Own power-on test enablement, debugging, and tool/flow reliability throughout the product lifecycle.
Location: Phoenix, Santa Clara, Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Architect a complete SoC-level DFT solution covering both synchronous and asynchronous designs.
  • •Lead flow development for scan insertion and compression at partition and SoC levels.
  • •Build a scalable framework across EDA tools, RTL, and emulation models to generate and validate high-quality test vectors pre-silicon.
  • •Collaborate with design architects to drive DFT/DFD/DFM features to ensure manufacturing readiness for HVM.
  • •Lead silicon power-on activities: enable tester content, debug failures, and maintain developed tools/flows.

Pay and Benefits

Salary: USD 141,910 - 269,100 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Bachelors and 6+ years OR Masters and 4+ years of hands-on DFT experience from architecture to silicon bring-up.
  • •6+ years architecting the entire DFT stack, including scan insertion, compression, and ATPG vector generation.
  • •4+ years of direct ownership of IP and SoC-level scan constructs (e.g., boundary scan/JTAG, TAP, BIST/MBIST).
  • •1+ year of experience debugging post-silicon and driving circuit changes for testability and reliability improvements.
  • •Experience with custom ASICS or AI/ML accelerator design and asynchronous architectures is preferred.
Experience:AI/ML acceleratorCustom ASICSNeuromorphic computing
Education:Bachelor's
Tech Stack:DFTDFXSoCScan insertionScan constructsCompressionATPGEDA toolsRTLEmulation modelsFault coverageJTAGTAPBISTMBISTSilicon power-onATPATESystem-VerilogSystem-C

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
Glassdoor
Glassdoor: 3.8
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