Senior Logic Design Engineer
NVIDIA
Santa Clara
Workplace: OnsiteFull timeUSD 136,000 - 218,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","RTL","DFT","Timing analysis","Lab bring-up","Python","C","Perl"]Senior Logic Design Engineer for the DGX FPGA Logic Team. Own and architect FPGA/CPLD designs, implement RTL in Verilog/SystemVerilog, and drive timing closure and validation from lab bring-up to system-wide bring-up across global sites (travel up to 20%). Collaborate with architecture, verification, and validation teams to ensure turnkey FPGA/ASIC development in data-center AI platforms.
