Principal SoC Design Engineer / SoC Lead

Neurophos
Austin, San Jose
Workplace: OnsiteFull timeUSD 225,000 - 300,000 annuallyFunction: Design (Product/UX/UI/Visual)Skills: ["Technical leadership","Cross-domain decision-making","Hands-on problem solving","Mentorship","Organization scaling"]

Lead full-chip or major-module integration for an advanced SoC at the intersection of silicon photonics and AI inference. Own and defend cross-domain system decisions across DFT, power, timing, and interconnect/data-fabric architecture, partnering with RTL, physical design, and verification to close system-level tradeoffs. Stay hands-on with the flow across levels and help scale the design organization by hiring and mentoring specialists.

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Neurophos
Neurophos
2 days ago

Principal SoC Design Engineer / SoC Lead

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Job Summary

Lead full-chip or major-module integration for an advanced SoC at the intersection of silicon photonics and AI inference. Own and defend cross-domain system decisions across DFT, power, timing, and interconnect/data-fabric architecture, partnering with RTL, physical design, and verification to close system-level tradeoffs. Stay hands-on with the flow across levels and help scale the design organization by hiring and mentoring specialists.
Location: Austin, San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Lead integration of the full chip or a major module/subsystem, including ownership of top-level integration flows.
  • •Make and own cross-domain technical decisions spanning system functionality, DFT, power, timing, and interconnect/data-fabric architecture.
  • •Partner across microarchitecture, RTL, physical design, verification, and DFT to resolve system-level tradeoffs.
  • •Go deep on needed domains while staying hands-on with the flow at every level.
  • •Help scale the design organization by hiring, mentoring, and growing engineers across specialty domains.

Pay and Benefits

Salary: USD 225,000 - 300,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceHsaPaid Leave401kEquityDentalVisionLife Insurance

Key Requirements

  • •Principal-level (or equivalent) technical leadership experience at a semiconductor or systems company with multiple full-chip tapeouts.
  • •Demonstrated breadth across domains, including closing timing on blocks and arguing interconnect architecture within the same cycle.
  • •Deep experience in CPU design or high-speed interconnect/data-fabric design (interconnect/data-fabric is especially central).
  • •Experience with advanced process nodes, high-bandwidth I/O, and large, physically big subsystem or full-chip designs.
  • •Comfort being evaluated as either an individual-contributor technical leader or a people manager.
Experience:SemiconductorsSystemsAI hardwareData-fabricHigh-speed interconnect
Skills:Technical leadershipCross-domain decision-makingHands-on problem solvingMentorshipOrganization scaling
Tech Stack:SoC integrationDFTPowerTimingInterconnectData-fabricRTLCadenceCerebrusAI-assisted EDA

Company Brief

Neurophos
Develops metamaterial-based photonic optical processing units (OPUs) to deliver high-performance, energy-efficient AI inference chips for datacenters, aiming to scale photonic compute to exaflop levels.
Industry: Deep Tech
Company Size: Small (11 to 50 employees)
Growth: Growth Stage Startup
Funding: Series A
Headquarters: Austin, United States
Founded: 2020
WebsiteLinkedIn