FPGA Verification Engineer

Anduril
United States
Workplace: OnsiteFull timeUSD 166,000 - 220,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: bachelorsSkills: ["Technical leadership","Cross-functional collaboration","Planning","Status reporting"]

Design and mature FPGA/ASIC verification for imaging hardware systems, working with an interdisciplinary team to build prototypes that support ground and flight testing. Architect verification environments, develop testbenches, and implement constrained-random, coverage, and assertion-based verification. Track code/functional coverage, recommend tools and practices for the ASIC/FPGA verification flow, and help lead verification planning, reporting, and engineering estimates.

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Anduril
Anduril
3 days ago

FPGA Verification Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Design and mature FPGA/ASIC verification for imaging hardware systems, working with an interdisciplinary team to build prototypes that support ground and flight testing. Architect verification environments, develop testbenches, and implement constrained-random, coverage, and assertion-based verification. Track code/functional coverage, recommend tools and practices for the ASIC/FPGA verification flow, and help lead verification planning, reporting, and engineering estimates.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Architect and design a verification environment using SystemVerilog and/or OVM/UVM.
  • •Create test plans and test cases, track code coverage, and track functional coverage.
  • •Develop testbenches to verify RTL blocks using VHDL or SystemVerilog.
  • •Recommend new tools and practices to continuously improve the ASIC/FPGA verification flow.
  • •Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status.

Pay and Benefits

Salary: USD 166,000 - 220,000 annually
Equity and Bonus:Equity

Key Requirements

  • •Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
  • •8+ years of experience developing HDL firmware for FPGA devices.
  • •Develop and simulate RTL designs using VHDL and/or Verilog in a professional FPGA/ASIC development environment.
  • •Design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
  • •Apply chip-level verification methodologies including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog).
Experience:8+ yearsDefense technologyFPGAASICRTL verification
Education:Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field
Skills:Technical leadershipCross-functional collaborationPlanningStatus reporting
Tech Stack:SystemVerilogOVM/UVMVHDLVerilogRTLGitSubversionUnix/LinuxCC++PythonPerlShell scriptingQuestaSimSynplifyQuartusVivadoConstrained-random testingFunctional coverageAssertion-based verification

Eligibility

Security Clearance:Secret

Company Brief

Anduril
Designs and builds advanced defense systems combining autonomous aircraft, sensors, and AI-driven software for military and national security applications, focused on modernizing battlefield capabilities and distributed sensing.
Industry: Defense Technology
Company Size: Enterprise (1,001+ employees)
Growth: Scaleup
Valuation: Unicorn (USD 1B+)
Funding: Series E+
Headquarters: Costa Mesa, United States
Founded: 2017
WebsiteLinkedIn