DFT Lead Engineer

Broadcom
San Jose
Workplace: OnsiteFull timeUSD 143,800 - 230,000 annuallyFunction: Administration & Executive AssistanceExperience: 10+ yearsEducation: bachelorsSkills: ["Problem solving","Debugging","Root cause analysis","Communication","Collaboration"]

Lead ASIC/SoC DFT programs end-to-end, defining DFT specifications and implementing/test-inserting scan and MBIST features through verification and release to production. Drive pattern generation, coverage improvement, and post-silicon debug/yield improvement, partnering with STA and design/test teams globally. Work on ATE bring-up validation, silicon failure analysis, customer interactions, and automation of DFT and test-vector generation flows for 7nm and beyond.

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FursaFursa
Broadcom
Broadcom
4 days ago

DFT Lead Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Lead ASIC/SoC DFT programs end-to-end, defining DFT specifications and implementing/test-inserting scan and MBIST features through verification and release to production. Drive pattern generation, coverage improvement, and post-silicon debug/yield improvement, partnering with STA and design/test teams globally. Work on ATE bring-up validation, silicon failure analysis, customer interactions, and automation of DFT and test-vector generation flows for 7nm and beyond.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance

Key Responsibilities

  • •Lead ASIC/SoC DFT programs from chip-level DFT specification through implementation, verification, and release to production.
  • •Implement and integrate DFT features including Scan, MBIST, TAP, LBIST, IO, SerDes, and other I/P DFT integration.
  • •Partner with STA and design engineers to achieve test mode timing closure and design closure for test.
  • •Generate, verify, and debug test vectors before tape release, including validation and debugging on ATE during silicon bring-up.
  • •Support silicon failure analysis, diagnostics, and yield improvement; collaborate with global teams and customers and automate DFT/test vector generation flows.

Pay and Benefits

Salary: USD 143,800 - 230,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEsppEapPaid HolidaysPaid LeaveParental Leave

Key Requirements

  • •Bachelors in Electrical/Electronic/Computer Engineering with 12+ years of relevant experience, or Masters with 10+ years relevant experience.
  • •Strong DFT background including IO/Analog DFT and ATPG, Scan, BIST, and related techniques.
  • •Experience with scan insertion/compression (e.g., DFT Compiler, Mentor TestKompress) and ATPG vector generation, simulation, and debugging (e.g., TetraMax, Fastscan).
  • •Experience with Verilog coding for testbench generation/simulation and memory BIST insertion/verification (SRAM, CAM, eDRAM, ROM).
  • •Knowledge of IEEE1149.1/IEEE1149.6 plus strong background on IEE1687, IJTAG, ICL, and PDL.
Experience:10+ yearsASICSoCSemiconductorsDFT7nm
Education:Bachelor's in Electrical/Electronic/Computer Engineering
Skills:Problem solvingDebuggingRoot cause analysisCommunicationCollaboration
Tech Stack:TCLPerlRubyPythonC++VerilogDFT CompilerMentor TestKompressTetraMaxFastscanIEEE1149.1IEEE1149.6IEEE1687IJTAGICLPDLATETessent SSNSerDesDDR

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn