Silicon Design Verification Senior Staff Engineer

AMD
Penang
Workplace: HybridFull timeMYR 185,500 - 265,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: mastersSkills: ["Communication","Team leadership","Technical discussion","Vocal communication"]

Lead PCIe SubSystem IP verification for AMD products, partnering with architects and design teams to deliver new verification components and cover new PCIe SS features end-to-end. Build and maintain IP-level verification environments, develop verification plans, and drive closure through tape-out readiness. Bring deep ASIC/SOC design verification experience with UVM and SystemVerilog/Verilog, plus PCIe and testbench architecture expertise for advanced interconnect validation.

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FursaFursa
AMD
AMD
5 days ago

Silicon Design Verification Senior Staff Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Lead PCIe SubSystem IP verification for AMD products, partnering with architects and design teams to deliver new verification components and cover new PCIe SS features end-to-end. Build and maintain IP-level verification environments, develop verification plans, and drive closure through tape-out readiness. Bring deep ASIC/SOC design verification experience with UVM and SystemVerilog/Verilog, plus PCIe and testbench architecture expertise for advanced interconnect validation.
Location: Penang
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Develop and update infrastructure and environment for IP-level design verification.
  • •Collaborate with Design and Architecture teams to develop new verification components.
  • •Own PCIe SS IP new-features verification plan and drive verification closure through readiness milestones.

Pay and Benefits

Salary: MYR 185,500 - 265,000 annually

Key Requirements

  • •8+ years of experience in digital ASIC/SOC design verification with solid ASIC verification flow knowledge and multiple ASIC tape-outs.
  • •Solid testbench architecture experience, including team leading experience.
  • •Strong knowledge of UVM, SystemVerilog, and Verilog (Verilog is a must).
  • •Preferred: PCIe background; also consider other high-speed IO protocol or Serdes PHY experience.
  • •Preferred: low power verification experience and/or formal verification knowledge; fluent written English for global technical discussion.
Experience:8+ yearsASIC design verificationPCIeSoCUVMHigh-speed IO
Education:Master's
Skills:CommunicationTeam leadershipTechnical discussionVocal communication
Languages:English
Tech Stack:UVMSystemVerilogVerilogPCIeASICSoCTestbench architectureFormal verificationSerdes PHY

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn