Tapeout Engineer

Texas Instruments
Bengaluru
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 2-5 yearsEducation: bachelorsSkills: []

Support TI’s Advanced Technology Development mask technology and pattern generation workflow, including converting test chip layouts into fracture data, preparing mask orders for vendor shipment, and generating reticle floorplan databases. Drive automations for PG/tapeout processes and collaborate with teams across ATD (process development, PDK), EDA, and business units to ensure required information is available. Apply consistent methodologies and best practices while maintaining high cycle time and quality.

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FursaFursa
Texas Instruments
Texas Instruments
2 months ago

Tapeout Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live

Job Summary

Support TI’s Advanced Technology Development mask technology and pattern generation workflow, including converting test chip layouts into fracture data, preparing mask orders for vendor shipment, and generating reticle floorplan databases. Drive automations for PG/tapeout processes and collaborate with teams across ATD (process development, PDK), EDA, and business units to ensure required information is available. Apply consistent methodologies and best practices while maintaining high cycle time and quality.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Convert product or technology development test chip layouts (LAFF, GDS) into fracture data.
  • •Prepare mask orders for shipment to vendors and manage integrity and archival of generated data (Mask Data Preparation).
  • •Generate reticle floorplan databases.
  • •Drive automations for use in the PG/tapeout process.
  • •Collaborate with and guide teams within ATD (process development, PDK), EDA, and business units to complete the PG process using consistent methodologies and best practices.

Key Requirements

  • •2–5 years of hardware engineering or related work experience, with a Bachelor’s/Master’s in Computer Science, Electrical/Electronic Engineering, or a related field.
  • •Understanding of layout and basics of the fabrication process (FEOL/BEOL).
  • •Knowledge of mask data tools such as Cadence Virtuoso, Pegasus designrev, and Mentor calibredrv.
  • •Maintain a high standard for cycle time and quality.
  • •Collaborate across teams to ensure necessary information is available to complete the PG (pattern generation) process.
Experience:2-5 yearsHardware engineering
Education:Bachelor's in Computer Science, Electrical/Electronic Engineering or related field
Tech Stack:FEOLBEOLLAFFGDSFracture dataMask data preparationReticle floorplan databasesPattern generation (PG)Tapeout processCadence VirtuosoPegasus designrevMentor calibredrvEDAPDK

Company Brief

Texas Instruments
Designs and manufactures semiconductors and analog chips used in industrial, automotive, personal electronics, communications, and enterprise systems. It is one of the world’s largest semiconductor companies, with a broad portfolio of embedded processing and power products.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Dallas, United States
Founded: 1930
WebsiteLinkedIn