AMD

2 weeks ago

Principal SoC I/O Performance Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Define and optimize I/O performance across next-generation SoCs, before silicon and after return from the fab. Set “fast enough” targets for bandwidth, latency, and QoS, build and extend performance models, and prove architectural tradeoffs with models, simulation, emulation, and post-silicon analysis. Partner across architecture, DV, firmware/software, validation, and platform teams to translate evidence into clear, actionable design decisions.

Location: Vancouver

Workplace: Hybrid

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Mid level

Key Responsibilities

•Define performance objectives, analysis methods, and signoff criteria for SoC I/O subsystems (bandwidth, latency, QoS, ordering, flow control, topology, congestion).
•Build, extend, and apply performance models to evaluate architectural options early and provide data-driven recommendations.
•Analyze performance data across models, simulation, emulation, firmware/software tests, traces, and counters, and correlate pre-silicon predictions with RTL/emulation/post-silicon results.
•Create reusable workloads, synthetic traffic patterns, trace-replay methods, benchmark flows, and KPI-correlation techniques that scale across teams.
•Partner with architecture, design, DV, emulation, firmware/software, validation, and platform teams to communicate tradeoffs in reviews, readouts, and written recommendations.

Key Requirements

•Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline (or equivalent practical experience).
•Familiarity with high-performance I/O, interconnect, memory, and coherency technologies such as PCIe, CXL, IOMMU/SMMU, UALink, Ethernet, InfiniBand, NVLink, UCIe, AXI, CHI, coherent fabrics, or DMA engines.
•Hands-on experience building or using performance models—analytical, event-driven, or transaction-level—using C++, Python, or SystemC/TLM.
•Comfort working with performance data from simulation, emulation, firmware/software tests, traces, counters, benchmarks, and silicon debug tools.
•Demonstrated technical leadership and cross-team influence using performance evidence to shape product or silicon direction.

Experience:SoCI/O architecturePerformance modelingDVEmulationPost-silicon validation

Education:Bachelor's in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline

Skills:Systems thinkingTechnical leadershipCross-team influenceData-driven decision-makingTechnical communication

Languages:English

Tech Stack:PCIeCXLIOMMUSMMUUALinkEthernetInfiniBandNVLinkUCIeAXICHICoherent fabricsDMAC++PythonSystemCTLMRTLDVSimulation

Company Brief

AMD

Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1969

Glassdoor: 3.9

Website LinkedIn

Loading job details...

Preparing the role view and application actions.

AMD