Lead Design Engineer

Cadence Design Systems
Seoul
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 6+ yearsSkills: ["Independent work","Teamwork","Self-motivation","Communication"]

Lead and/or participate in ASIC physical design implementation for Cadence Korea, covering floorplanning through tapeout-critical closure activities. Own work across power grid design, place & route, clock tree synthesis, timing closure, and power/signal integrity signoff, including DRC/LVS, EM/IR, and DFM closure. Partner closely with RTL design teams and help advance next-generation physical design methods, flows, and methodology development.

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Cadence Design Systems
Cadence Design Systems
10 hours ago

Lead Design Engineer

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Last checked: 10 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Lead and/or participate in ASIC physical design implementation for Cadence Korea, covering floorplanning through tapeout-critical closure activities. Own work across power grid design, place & route, clock tree synthesis, timing closure, and power/signal integrity signoff, including DRC/LVS, EM/IR, and DFM closure. Partner closely with RTL design teams and help advance next-generation physical design methods, flows, and methodology development.
Location: Seoul
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Lead physical design implementation projects, including floorplanning, power grid design, place and route, and clock tree synthesis.
  • •Drive timing closure and power/signal integrity signoff, including power verification and related analyses.
  • •Perform and validate physical verification activities (DRC/LVS/Antenna) and EM/IR signoff, including EM/IR-drop and crosstalk analysis.
  • •Support DFM closure and closure activities across low-power and high-speed designs on advanced technology nodes.
  • •Participate in or lead next-generation physical design methodology and flow development, working closely with RTL teams to ensure successful tapeouts.

Key Requirements

  • •6+ years of experience with ASIC design flow and hierarchical physical design strategies, methodologies, and deep sub-micron considerations.
  • •Solid knowledge of low power design, DFT, and static timing analysis with closure, including data skew balancing and duty cycle adjustment.
  • •Experience with EM/IR-drop and crosstalk analysis, formal verification, physical verification (DRC/LVS/Antenna), and EM/IR signoff.
  • •Strong understanding of DFM and physical implementation/verification practices such as placement and route (P&R).
  • •Ability to take ownership of technical tasks independently and to work hands-on at all design levels.
Experience:6+ yearsASIC design
Skills:Independent workTeamworkSelf-motivationCommunication
Languages:English
Tech Stack:ASICPhysical designFloorplanningPower grid designPlace and routeClock tree synthesisTiming closurePower/signal integrity signoffPhysical verificationDRCLVSAntennaEM/IR signoffDFM closureLow power designDFTStatic timing analysisData skew balancingDuty cycle adjustmentEM/IR-drop analysis

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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