Memory Interface PHY IP, Design Engineering Architect

Design Engineering Architect focuses on PHY architecture development for memory interface IPs (DDR, LPDDR) and JEDEC standards, acting as a customer-facing technical architect during pre-sales and post-delivery support. The role collaborates with Sales, Marketing, and Program teams, provides expert IP support, and guides cross-functional teams to ensure architectural intent is implemented while influencing product roadmap with a strong emphasis on communication and technical ownership.