ASIC Floorplan Design Engineer - New College Grad 2026

NVIDIA
Santa Clara
Workplace: OnsiteFull timeUSD 116,000 - 218,500 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Communication","Interpersonal skills","Teamwork","Collaboration"]

Develop and optimize ASIC floorplans during early chip development for leading SoCs and GPUs. Partner with architects, design leads, physical design leads, and package leads to run area review processes and identify area/interconnect/floorplan improvements. Help resolve timing and routing congestion through early design and implementation decisions, and build tools to improve infrastructure that accelerates chip area and speed execution.

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FursaFursa
NVIDIA
NVIDIA
1 week ago

ASIC Floorplan Design Engineer - New College Grad 2026

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Develop and optimize ASIC floorplans during early chip development for leading SoCs and GPUs. Partner with architects, design leads, physical design leads, and package leads to run area review processes and identify area/interconnect/floorplan improvements. Help resolve timing and routing congestion through early design and implementation decisions, and build tools to improve infrastructure that accelerates chip area and speed execution.
Location: Santa Clara
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Graduate level

Key Responsibilities

  • •Work with architects and multiple design leads to develop and optimize floorplans during early chip development.
  • •Drive the area review process and collaborate with the ASIC design team to find floorplan, area, and interconnect improvement opportunities.
  • •Address timing and routing congestion by influencing early design and physical implementation decisions.
  • •Build tools and improve existing infrastructure to optimize chip area and speed of execution.
  • •Coordinate across ASIC design stakeholders to improve early design and physical implementation outcomes.

Pay and Benefits

Salary: USD 116,000 - 218,500 annually

Key Requirements

  • •Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering (or equivalent experience).
  • •Strong hardware engineering background with a concentration in VLSI and/or Computer Architecture.
  • •Experience with Verilog or SystemVerilog (or similar HVL).
  • •Experience with CAD and physical design methodologies, including chip floorplanning, power/clock distribution, packaging, P&R, and timing closure.
  • •Python, Perl, and C/C++ programming experience.
Experience:ASIC designVLSIComputer architecturePhysical design
Education:Master's in Electrical Engineering, Computer Science, or Computer Engineering
Skills:CommunicationInterpersonal skillsTeamworkCollaboration
Tech Stack:ASICFloorplanningVLSIComputer ArchitectureVerilogSystemVerilogHVLCADPhysical designPower/clock distributionPackagingP&RTiming closurePythonPerlC/C++TimingRouting

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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