Lead Product Engineer

Cadence Design Systems
Taiwan
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceSkills: ["Communication","Problem-solving","Collaboration","Ownership","Self-driven"]

Drive best-in-class static timing analysis (STA) solutions by translating customer requirements into precise product specifications and acting as a technical bridge to R&D. You’ll leverage deep STA signoff expertise (including advanced signoff methodologies and constraint modeling), support deployments and customer enablement (evaluations, benchmarking, and flow recommendations), and continuously improve tool quality, usability, and success across real customer designs.

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Cadence Design Systems
Cadence Design Systems
2 days ago

Lead Product Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Drive best-in-class static timing analysis (STA) solutions by translating customer requirements into precise product specifications and acting as a technical bridge to R&D. You’ll leverage deep STA signoff expertise (including advanced signoff methodologies and constraint modeling), support deployments and customer enablement (evaluations, benchmarking, and flow recommendations), and continuously improve tool quality, usability, and success across real customer designs.
Location: Taiwan
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance

Key Responsibilities

  • •Demonstrate deep hands-on STA expertise, including advanced signoff methodologies and constraint modeling.
  • •Translate customer pain points and use cases into detailed, efficient product specifications and implementable requirements.
  • •Collaborate with R&D on feature development, enhancements, and bug fixes for timing signoff solutions.
  • •Support tool deployment and customer enablement through evaluations, benchmarking, and flow recommendations.
  • •Proactively identify tool gaps, propose enhancements, and validate solutions across real customer designs.

Key Requirements

  • •Hands-on expertise in static timing analysis (STA), including advanced signoff methodologies (timing, SI, OCV/POCV, AOCV, MPW, derates, CDC/clocking, hierarchical design closure, and constraint modeling).
  • •Strong understanding of STA tools and familiarity with industry-standard signoff flows.
  • •Experience with Tempus and/or PrimeTime; understanding timing constraints (SDC) and path-based analysis.
  • •Scripting skills for automation and flow optimization (Tcl, with Python preferred).
  • •Knowledge of VLSI design flows (front-end to signoff) is preferred, with clear communication of complex technical concepts.
Experience:VLSIEDAStatic timing analysisSignoffProduct deployment
Skills:CommunicationProblem-solvingCollaborationOwnershipSelf-driven
Tech Stack:Static Timing Analysis (STA)TempusPrimeTimeTclPythonSDCConstraint modeling

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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