Mixed Signal Logic Design Engineer

Own mixed-signal and high-speed IP logic design by defining microarchitecture and implementing RTL in SystemVerilog. Collaborate with architecture and system teams to optimize power, performance, and area, while building automation flows and running RTL quality checks (lint, CDC, synthesis QA). Perform power/performance analysis, resolve verification and RTL issues, and support SoC integration. Drive innovation through automated coverage closure and timing convergence.