Cisco

1 month ago

Signal & Power Integrity Hardware ASIC Simulation Engineer (Hybrid)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Seeking an experienced Signal and Power Integrity Engineer to develop, verify, and optimize ASIC packaging for Cisco Silicon One platforms. You will analyze SI/PI across interposers, substrates, and PCBs, design high-volume ASIC packages, and collaborate with layout and system teams to meet power, performance, and area targets in a hybrid-remote Cisco environment.

Location: San Jose, California

Workplace: Hybrid

Employment Type: Full time

Job Function: Energy & Utilities Operations

Key Responsibilities

•Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
•Analyze substrate signal integrity and power integrity, collaborating with the layout team to optimize interposer, substrate, and PCB solutions.
•Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
•Collaborate with system partners, vendors, and design leads to ensure combined power and signal integrity and resolve complex technical issues.
•Lead layout reviews and physical validation to ensure signal performance and manage crosstalk mitigation.

Pay and Benefits

Salary: USD 165,000 - 241,400 annually

Equity and Bonus:Equity

Perks:Health InsuranceDentalVision401kRsusEquityAnnual BonusParental LeavePaid LeaveSick TimeVolunteer Time

Key Requirements

•Bachelor's degree in Electrical Engineering with 6+ years of relevant SI/PI experience, or Master's degree with 3+ years, or PhD with 1+ year of relevant experience.
•High-Speed Architecture & Theory: Transmission Line Theory, electromagnetics, S-parameters, impedance networks applied to 56G PAM4 SerDes architectures, channel modeling, BER prediction.
•SI/PI Simulation Proficiency: Pre- and post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
•Layout Review & Physical Validation: Detailed layout reviews and physical design validation using Cadence APD and Ansys EM flows to mitigate crosstalk.
•Circuit Analysis: Working knowledge of SPICE for circuit-level analysis and performance validation.

Experience:6+ yearsSemiconductorASICSiliconHardwareElectronic design

Education:Bachelor's

Skills:CommunicationProblem-solvingTeam collaborationVerbal communicationWritten communication

Tech Stack:Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM flowsSPICEHBMDie-to-die interfacesUCIeCoWoSEMIBInterposer2.5DPAM4SerDes

Company Brief

Cisco

Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor

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Cisco

1 month ago

Signal & Power Integrity Hardware ASIC Simulation Engineer (Hybrid)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: San Jose, California

Workplace: Hybrid

Employment Type: Full time

Job Function: Energy & Utilities Operations

Key Responsibilities

•Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
•Analyze substrate signal integrity and power integrity, collaborating with the layout team to optimize interposer, substrate, and PCB solutions.
•Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
•Collaborate with system partners, vendors, and design leads to ensure combined power and signal integrity and resolve complex technical issues.
•Lead layout reviews and physical validation to ensure signal performance and manage crosstalk mitigation.

Pay and Benefits

Salary: USD 165,000 - 241,400 annually

Equity and Bonus:Equity

Perks:Health InsuranceDentalVision401kRsusEquityAnnual BonusParental LeavePaid LeaveSick TimeVolunteer Time

Key Requirements

•Bachelor's degree in Electrical Engineering with 6+ years of relevant SI/PI experience, or Master's degree with 3+ years, or PhD with 1+ year of relevant experience.
•High-Speed Architecture & Theory: Transmission Line Theory, electromagnetics, S-parameters, impedance networks applied to 56G PAM4 SerDes architectures, channel modeling, BER prediction.
•SI/PI Simulation Proficiency: Pre- and post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
•Layout Review & Physical Validation: Detailed layout reviews and physical design validation using Cadence APD and Ansys EM flows to mitigate crosstalk.
•Circuit Analysis: Working knowledge of SPICE for circuit-level analysis and performance validation.

Experience:6+ yearsSemiconductorASICSiliconHardwareElectronic design

Education:Bachelor's

Skills:CommunicationProblem-solvingTeam collaborationVerbal communicationWritten communication

Tech Stack:Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM flowsSPICEHBMDie-to-die interfacesUCIeCoWoSEMIBInterposer2.5DPAM4SerDes

Company Brief

Cisco

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor