High Speed IO Validation Engineer

NVIDIA
India
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: bachelorsSkills: ["Root-cause analysis","Cross-functional collaboration","Debugging","Test planning","Automation"]

Own end-to-end characterization and validation of NVIDIA high-speed I/Os (PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet) from silicon die through package and board. Build validation test plans (bring-up, corner qualification, stress, DOE) across PVT and platform variables, perform power characterization and optimization, and lead root-cause analysis for HSIO bugs. Translate rack failures into silicon/board reproducers and develop automation and margin-tracking infrastructure to improve yield and coverage.

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FursaFursa
NVIDIA
NVIDIA
1 month ago

High Speed IO Validation Engineer

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Last checked: 17 hours agoStatus: Live

Job Summary

Own end-to-end characterization and validation of NVIDIA high-speed I/Os (PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet) from silicon die through package and board. Build validation test plans (bring-up, corner qualification, stress, DOE) across PVT and platform variables, perform power characterization and optimization, and lead root-cause analysis for HSIO bugs. Translate rack failures into silicon/board reproducers and develop automation and margin-tracking infrastructure to improve yield and coverage.
Location: India
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Own end-to-end characterization and validation of high-speed IO (PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet) from silicon die through package and board.
  • •Develop and execute validation test plans for HSIO features, including bring-up, corner qualification, stress, productization, and DOE across PVT, board, thermal, cable/connector, and firmware variables.
  • •Drive power characterization and optimization across IO interconnects using workload-representative stimuli (MLPerf-class patterns), and feed trade-offs into design, firmware, and binning.
  • •Lead systematic root-cause analysis for complex HSIO bugs across silicon, package, board, firmware, and driver, and convert rack-observed failures into silicon/board reproducers.
  • •Develop validation methodologies and automation/margin-tracking infrastructure to improve efficiency and coverage as platform complexity grows.

Key Requirements

  • •BS or MS in Electrical or Computer Engineering (or equivalent) with 8+ years in post-silicon HSIO validation or characterization.
  • •Deep understanding of high-speed serial link protocols (PCIe Gen5+, NVLink, NVLink-C2C, UCIe, CXL) and SERDES architecture, including equalization and link training.
  • •Strong signal integrity and power integrity fundamentals (S-parameters, eye diagrams, channel margin, jitter decomposition) with validation across silicon and platform boundaries.
  • •Hands-on lab experience with DSO, BERT, VNA, protocol/logic analyzers, and TDR, plus DOE/shmoo/margin trending.
  • •Experience with Python-based test automation and cross-functional debug across chip, package, board, firmware, driver, and system teams.
Experience:8+ yearsPost-silicon validationHigh-speed IOSERDESSilicon characterization
Education:Bachelor's in Electrical or Computer Engineering
Skills:Root-cause analysisCross-functional collaborationDebuggingTest planningAutomation
Tech Stack:PCIePCIe Gen5+PCIe Gen6NVLinkNVLink-C2CUCIeUSBUFSEthernetCXLSERDESEqualizationLink trainingSignal integrityPower integrityS-parametersEye diagramsChannel marginCrosstalkReturn loss

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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