Cadence Design Systems

1 month ago

Design Engineering Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Design verification for advanced IPs in Cadence’s IP group, driving UVM/Formal verification and possible emulation qualification for PCIe, CCIX, CXL, USB, Ethernet, and other interfaces. Lead verification strategy, test plans, and hands-on debugging in a collaborative, cross-geography environment with a strong emphasis on quality and timely delivery.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

•Verify Serial and Interface Design IPs and develop robust UVM testbenches to verify the design IPs.
•Formulate and implement detailed verification strategy and test plans for IP blocks.
•Collaborate across functions and geographies to communicate project status, issues, and progress.
•Possibly perform Formal verification of complex design modules and participate in Emulation qualification of design IPs.
•Demonstrate strong problem solving, analytical and debugging skills to ensure timely high-quality delivery.

Key Requirements

•B.Tech/M.Tech with 18+ years of relevant experience.
•Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C).
•UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
•In addition to UVM functional verification, role could involve Formal verification of complex design modules.
•In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.

Experience:18+ yearsSemiconductorsEDAIP

Skills:UVMTestbenchVerificationDebugCommunicationTeamworkProblem-solvingPresentation

Tech Stack:UVMFormal verificationEmulationPCIeCCIXCXLUSBEthernetSATASASUFSSPIHDMIMIPII3C

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

1 month ago

Design Engineering Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

•Verify Serial and Interface Design IPs and develop robust UVM testbenches to verify the design IPs.
•Formulate and implement detailed verification strategy and test plans for IP blocks.
•Collaborate across functions and geographies to communicate project status, issues, and progress.
•Possibly perform Formal verification of complex design modules and participate in Emulation qualification of design IPs.
•Demonstrate strong problem solving, analytical and debugging skills to ensure timely high-quality delivery.

Key Requirements

•B.Tech/M.Tech with 18+ years of relevant experience.
•Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C).
•UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
•In addition to UVM functional verification, role could involve Formal verification of complex design modules.
•In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.

Experience:18+ yearsSemiconductorsEDAIP

Skills:UVMTestbenchVerificationDebugCommunicationTeamworkProblem-solvingPresentation

Tech Stack:UVMFormal verificationEmulationPCIeCCIXCXLUSBEthernetSATASASUFSSPIHDMIMIPII3C

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor