SoC DFX Staff Engineer

AMD
Markham, Vancouver, Ottawa, Calgary
Workplace: HybridFull timeCAD 112,000 - 192,000 annuallyFunction: QA, Test & Release EngineeringEducation: bachelorsSkills: ["Collaboration","Communication","Problem-solving","Ownership","Adaptability"]

Design and verify robust Design for Test (DFT) and Design for Debug (DFD) solutions for complex, high-performance SoCs. Partner with architecture, RTL, firmware, and verification teams to integrate DFX features, build directed/random verification tests, and debug failures to root cause. Create test plan documentation, estimate test development effort, and use functional/code coverage metrics to improve test quality across silicon validation and bring-up.

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FursaFursa
AMD
AMD
2 days ago

SoC DFX Staff Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Design and verify robust Design for Test (DFT) and Design for Debug (DFD) solutions for complex, high-performance SoCs. Partner with architecture, RTL, firmware, and verification teams to integrate DFX features, build directed/random verification tests, and debug failures to root cause. Create test plan documentation, estimate test development effort, and use functional/code coverage metrics to improve test quality across silicon validation and bring-up.
Location: Markham, Vancouver, Ottawa, Calgary
Workplace: Hybrid
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Mid level

Key Responsibilities

  • •Collaborate with architects, hardware engineers, and firmware engineers to understand new DFX features to be designed and verified.
  • •Design and integrate DFX logic in complex SoCs as part of the full product lifecycle.
  • •Create test plan documentation covering interactions across hardware, firmware, and software driver use cases.
  • •Estimate time and build directed and random verification tests for new DFX features.
  • •Debug test failures to determine root cause and resolve design defects; adjust tests/constraints to meet coverage requirements.

Pay and Benefits

Salary: CAD 112,000 - 192,000 annually

Key Requirements

  • •Experience designing and verifying DFT (Design for Test) and DFD (Design for Debug) architectures, designs, and verification.
  • •Hands-on knowledge of JTAG, LBIST, MBIST, scan, and ATPG, including test pattern generation and bring-up/debug on ATE.
  • •Familiarity with Tessent tools (Scan and ATPG) and experience with post-silicon bring-up.
  • •Experience with IP-level and ASIC verification, including debugging firmware and RTL using simulation tools.
  • •Working knowledge of Verilog, SystemVerilog, SystemC, and C++ plus UVM concepts; scripting experience (Perl, Ruby, Makefile, shell) is preferred.
Experience:SoCDFTDFDASIC verificationPost-silicon bring-upUVM
Education:Bachelor's in Electrical Engineering, Computer Engineering, or related field
Skills:CollaborationCommunicationProblem-solvingOwnershipAdaptability
Tech Stack:DFTDFDJTAGLBISTMBISTScanATPGTessentTest pattern generationATEPost-silicon bring-upIP-level verificationASIC verificationVerilogSystemVerilogSystemCC++UVMStatic timing analysisConstraints

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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