4 months ago

Applied ML – Functional Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Pre-silicon verification engineer applying machine learning to streamline formal and UVM-based verification, working on AI-enabled verification methodologies within Cadence’s ChipStack AI Super Agent team in San Jose. You’ll collaborate with ML engineers and software developers to design, implement, and validate AI-powered verification workflows, engaging with customers and advancing AI-driven EDA tools across design and verification lifecycles.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Software Engineering

Key Responsibilities

•Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
•Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
•Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.
•Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.
•Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.

Key Requirements

•BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
•Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM
•Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools
•Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC)
•Strong programming skills in Verilog, System Verilog and Python

Experience:10+ yearsSemiconductorEDAAI in hardware verification

Education:Bachelor's

Skills:CommunicationTeamworkProblem solvingSelf-motivatedProactive learning

Tech Stack:VerilogSystemVerilogPythonJasperXceliumIMCUVMOVMFormalLLMsRAGRL

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

Loading job details...

Preparing the role view and application actions.

Cadence Design Systems

4 months ago

Applied ML – Functional Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Software Engineering

Key Responsibilities

•Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
•Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
•Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.
•Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.
•Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.

Key Requirements

•BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
•Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM
•Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools
•Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC)
•Strong programming skills in Verilog, System Verilog and Python

Experience:10+ yearsSemiconductorEDAAI in hardware verification

Education:Bachelor's

Skills:CommunicationTeamworkProblem solvingSelf-motivatedProactive learning

Tech Stack:VerilogSystemVerilogPythonJasperXceliumIMCUVMOVMFormalLLMsRAGRL

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor