Lead ASIC Design Engineer

Broadcom
San Jose
Workplace: OnsiteFull timeUSD 143,800 - 230,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["Communication","Leadership","Problem-solving"]

Hands-on Principal Digital Design Engineer serving as Chip Lead for next-generation silicon. Own top-level digital architecture, microarchitecture, and full chip integration, guiding cross-disciplinary teams (analog, physical design, verification) from definition to tape-out. Lead RTL/ front-end flows, timing, IP integration, silicon validation, and mentor junior engineers to meet strict PPA targets and successful first-pass tape-outs.

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FursaFursa
Broadcom
Broadcom
3 months ago

Lead ASIC Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 33 days agoStatus: Live

Job Summary

Hands-on Principal Digital Design Engineer serving as Chip Lead for next-generation silicon. Own top-level digital architecture, microarchitecture, and full chip integration, guiding cross-disciplinary teams (analog, physical design, verification) from definition to tape-out. Lead RTL/ front-end flows, timing, IP integration, silicon validation, and mentor junior engineers to meet strict PPA targets and successful first-pass tape-outs.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Technical Ownership: Serve as the central Chip Lead, defining top-level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle.
  • •Cross-Discipline Alignment: Bridge Logic Design, Physical Design, Architecture, and DV to meet PPA targets.
  • •Tape-Out Delivery: Own and drive the final tape-out sign-off checklist and coordinate across teams for a clean handoff to foundry.
  • •Mentorship & Culture: Provide technical guidance, code reviews, and architectural mentorship to mid-level and junior engineers.
  • •Silicon Validation: Collaborate with post-silicon validation and software teams during initial chip bring-up and lab debug phases.

Pay and Benefits

Salary: USD 143,800 - 230,000 annually
Equity and Bonus:Equity
Perks:Health Insurance401kRsusEquityEsppPaid LeaveMedicalDentalVisionLife InsuranceWellness StipendDep Mat

Key Requirements

  • •Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • •Experience: 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.
  • •RTL Mastery: Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.
  • •Tool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).
  • •Silicon Track Record: Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies.
Experience:12+ yearsSemiconductorASICSoCElectronics
Education:Bachelor's
Skills:CommunicationLeadershipProblem-solving
Tech Stack:SystemVerilogVerilogDesign CompilerGenusPrimeTimeTempusLintSpyGlassJasperGoldSDCCDC

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn