ASIC Design Engineer - Networking/ DPU/ AI Systems

AMD
Santa Clara
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Collaboration","Ownership","Problem-solving","Leadership"]

Senior ASIC Design Engineer responsible for architecting and delivering high-speed DPU ASIC blocks for AI networking workloads, guiding the full development lifecycle from RTL to tapeout and mass production, and collaborating across verification, modeling, software and hardware teams to optimize performance, power, and area.

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FursaFursa
AMD
AMD
5 months ago

ASIC Design Engineer - Networking/ DPU/ AI Systems

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 43 minutes agoStatus: Live

Job Summary

Senior ASIC Design Engineer responsible for architecting and delivering high-speed DPU ASIC blocks for AI networking workloads, guiding the full development lifecycle from RTL to tapeout and mass production, and collaborating across verification, modeling, software and hardware teams to optimize performance, power, and area.
Location: Santa Clara
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Architect and design key blocks for next-generation DPU ASICs targeting AI networking workloads.
  • •Contribute across the full ASIC development lifecycle, including architecture definition, microarchitecture/RTL design, design reviews, implementation, tapeout, silicon bring-up, and production ramp.
  • •Collaborate on advanced network processing engines, including P4-based, protocol-independent packet processing solutions.
  • •Design and implement high-speed, complex ASIC blocks for networking and data movement applications; ensure functional correctness and system-level performance with verification, modeling, software and hardware teams.
  • •Produce high-quality design documentation and participate in technical reviews; debug and resolve issues across simulation, emulation, lab bring-up, and post-silicon phases.

Key Requirements

  • •Seasoned ASIC design experience.
  • •Proven hands-on experience developing high-speed, complex ASICs.
  • •Strong RTL design skills with Verilog and SystemVerilog; experience across RTL to tapeout to mass production.
  • •Solid background in networking and packet-processing architectures; experience collaborating with verification, modeling, software and hardware teams.
  • •Bachelor’s or Master’s degree in Electrical Engineering or related field; location: Santa Clara, CA; this role is not eligible for visa sponsorship.
Experience:ASICNetworkingDPUAI systemsNoC
Education:Bachelor's in Electrical Engineering
Skills:CommunicationCollaborationOwnershipProblem-solvingLeadership
Languages:English
Tech Stack:VerilogSystemVerilogCC++PythonTclShellNoCAXIAMBA

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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