ASIC Design Engineer - Networking/ DPU/ AI Systems
AMD
Santa Clara
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Collaboration","Ownership","Problem-solving","Leadership"]Senior ASIC Design Engineer responsible for architecting and delivering high-speed DPU ASIC blocks for AI networking workloads, guiding the full development lifecycle from RTL to tapeout and mass production, and collaborating across verification, modeling, software and hardware teams to optimize performance, power, and area.

