Cadence Design Systems

3 months ago

Prinicipal Customer Engagement Engineer - PDK

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Join Cadence as a Principal Customer Engagement Engineer for PDK, leveraging 6+ years in IC design or electronics to engage with customers, support analog design flows, and optimize post-layout processes. Work with foundries, use scripting (PERL/TCL/SKILL), and collaborate with cross‑functional teams to advance semiconductor design flows and PDK concepts.

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Engage with customers to understand their design challenges and provide technical guidance on PDK-based IC design workflows.
•Assist in analog design flows, including circuit and layout design, DRC/LVS/dummy fill, and post-layout RC extraction processes.
•Leverage Spice models and simulations to support design verification and debugging for customers and foundries.
•Collaborate with foundry partners and Cadence teams to optimize manufacturing processes and variability considerations.
•Utilize scripting (PERL/TCL/SKILL) and Cadence PAS/Pcell tools to enhance design flows and customer delivered solutions.

Key Requirements

•Bachelor’s degree is required, with 6+ years of experience in IC design, electronic engineering, or computer science–related applications.
•Familiar with analog design flows, including circuit and layout design, physical verification (DRC/LVS/Dummy Fill), and post-layout RC extraction flows.
•Solid understanding of Spice models and simulation flows is a strong plus.
•Basic understanding of semiconductor manufacturing processes (e.g., CMOS process fundamentals, PDK concepts, variability considerations).
•Proficient in programming languages, including PERL/TCL/SKILL, with experience using Cadence PAS/Pcell Designer tools is a plus.

Experience:6+ yearsIC designSemiconductorFoundryElectronic engineering

Education:Bachelor's

Skills:PERLTCLSKILLCadence PASPcell DesignerSpiceRC extractionDC/verification

Tech Stack:SpiceCMOSPDKPERLTCLSKILLCadence PASPcell Designer

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

3 months ago

Prinicipal Customer Engagement Engineer - PDK

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Engage with customers to understand their design challenges and provide technical guidance on PDK-based IC design workflows.
•Assist in analog design flows, including circuit and layout design, DRC/LVS/dummy fill, and post-layout RC extraction processes.
•Leverage Spice models and simulations to support design verification and debugging for customers and foundries.
•Collaborate with foundry partners and Cadence teams to optimize manufacturing processes and variability considerations.
•Utilize scripting (PERL/TCL/SKILL) and Cadence PAS/Pcell tools to enhance design flows and customer delivered solutions.

Key Requirements

•Bachelor’s degree is required, with 6+ years of experience in IC design, electronic engineering, or computer science–related applications.
•Familiar with analog design flows, including circuit and layout design, physical verification (DRC/LVS/Dummy Fill), and post-layout RC extraction flows.
•Solid understanding of Spice models and simulation flows is a strong plus.
•Basic understanding of semiconductor manufacturing processes (e.g., CMOS process fundamentals, PDK concepts, variability considerations).
•Proficient in programming languages, including PERL/TCL/SKILL, with experience using Cadence PAS/Pcell Designer tools is a plus.

Experience:6+ yearsIC designSemiconductorFoundryElectronic engineering

Education:Bachelor's

Skills:PERLTCLSKILLCadence PASPcell DesignerSpiceRC extractionDC/verification

Tech Stack:SpiceCMOSPDKPERLTCLSKILLCadence PASPcell Designer

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor