Physical Design Engineer - Full Chip Implementation

Etched
San Jose
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsSkills: ["Deeply creative","Ability to think from first principles"]

Own full-chip physical design implementation for frontier inference clusters, from floorplanning and P&R through clocking, timing analysis, physical verification, and sign-offs to GDSII completion. Drive aggressive PPA optimization and timing closure using PD flows, manage MMMC and hierarchical timing budgeting, and lead functional/timing ECO closure. Collaborate with RTL designers to rapidly debug and resolve DRC/LVS/ERC issues and complete repeatable, tapeout-ready verification methodology.

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FursaFursa
Etched
Etched
1 month ago

Physical Design Engineer - Full Chip Implementation

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Source: Company careers pageValidated by: Fursa AI
Last checked: 17 hours agoStatus: Live

Job Summary

Own full-chip physical design implementation for frontier inference clusters, from floorplanning and P&R through clocking, timing analysis, physical verification, and sign-offs to GDSII completion. Drive aggressive PPA optimization and timing closure using PD flows, manage MMMC and hierarchical timing budgeting, and lead functional/timing ECO closure. Collaborate with RTL designers to rapidly debug and resolve DRC/LVS/ERC issues and complete repeatable, tapeout-ready verification methodology.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own full-chip implementation from synthesis through GDSII completion, including floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs.
  • •Drive full-chip clocking across all PVT corners and modes and manage MMMC timing closure at the top level.
  • •Own timing constraints and hierarchical timing budgeting between top level and blocks.
  • •Lead functional and timing ECO closure, achieve final timing signoff, and support tapeout readiness.
  • •Own end-to-end physical verification closure and debug PV violations by fixing issues directly in layout using Innovus.

Pay and Benefits

Perks:Health InsuranceDentalVisionMedical CreditHousing Subsidy

Key Requirements

  • •10+ years of experience with chip planning, top-level PD, and floorplanning.
  • •Top-level and full-chip closure experience on advanced process nodes (5nm and below).
  • •Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows.
  • •Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff.
  • •Experience with Pegasus or Calibre for physical verification signoff and hierarchical timing budgeting/ECO closure.
Experience:10+ yearsSemiconductorAI hardwareInferenceRTL-to-GDSIIAdvanced process nodes
Skills:Deeply creativeAbility to think from first principles
Tech Stack:InnovusGenusFusion CompilerPrimeTimeTempusPegasusCalibreMMMCGDSIIPPADRCLVSERCPythonRTLECO

Company Brief

Etched
Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Early Stage Startup
Valuation: Unicorn (USD 1B+)
Funding: Series A
Headquarters: San Jose, United States
Founded: 2022
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