Physical Design Engineer - Full Chip Implementation

Own full-chip physical design implementation for frontier inference clusters, from floorplanning and P&R through clocking, timing analysis, physical verification, and sign-offs to GDSII completion. Drive aggressive PPA optimization and timing closure using PD flows, manage MMMC and hierarchical timing budgeting, and lead functional/timing ECO closure. Collaborate with RTL designers to rapidly debug and resolve DRC/LVS/ERC issues and complete repeatable, tapeout-ready verification methodology.