Design Verification Engineer
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Collaboration","Technical leadership","Mentorship","Debugging","Risk assessment"]Own functional verification for block-level and full-chip designs from specification through tape-out. Build and maintain verification plans, test strategies, and coverage models, architecting SystemVerilog/UVM testbenches with vectors and assertions. Run directed and constrained-random simulations, debug functional failures, and drive functional/code/assertion coverage closure while partnering with design engineers and global cross-functional teams to resolve risks and issues.
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